100336

Low Power 4-Stage Counter/Shift Register

General Description

The 100336 operates as either a modulo-16 up/down

counter or as a 4-bit bidirectional shift register. Three Select

(S

Function Select table. Two Count Enable (CEP, CET) inputs

are provided for ease of cascading in multistage counters.

One Count Enable (CET) input also doubles as a Serial Data

(D

is the Serial Data input. In counting operations the Terminal

Count (TC) output goes LOW when the counter reaches 15

in the count/up mode or 0 (zero) in the count/down mode. In

the shift modes, the TC output repeats the Q

dual nature of this TC/Q

means that one interconnection from one stage to the next

higher stage serves as the link for multistage counting or

shift-up operation. The individual Preset (P

to enter data in parallel or to preset the counter in program-

mable counter applications. A HIGH signal on the Master Re-

set (MR) input overrides all other inputs and asynchronously

clears the flip-flops. In addition, a synchronous clear is pro-

vided, as well as a complement function which synchro-

nously inverts the contents of the flip-flops. All inputs have 50

k

Ω pull-down resistors.

Features

n 40% power reduction of the 100136

n 2000V ESD protection

n Pin/function compatible with 100136

n Voltage compensated operating range = −4.2V to −5.7V

n Standard Microcircuit Drawing

(SMD) 5962-9230601

Logic Symbol

Pin

Names

Description

CP

Clock Pulse Input

CEP

Count Enable Parallel Input (Active LOW)

D

Serial Data Input/Count Enable

Trickle Input (Active LOW)

S

Select Inputs

MR

Master Reset Input

P

Preset Inputs

D

3

Serial Data Input

TC

Terminal Count Output

Q

Data Outputs

Q

Complementary Data Outputs

DS100307-1

August 1998

© 1998 National Semiconductor Corporation

DS100307

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