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TCC-206 Datasheet(PDF) 10 Page - ON Semiconductor |
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TCC-206 Datasheet(HTML) 10 Page - ON Semiconductor |
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10 / 33 page  TCC−206 www.onsemi.com 10 Table 10. 3−WIRE SERIAL INTERFACE SPECIFICATION (TA = −30 to +85°C; 2.3 V < AVDD < 5.5 V; VIO = 1.8 V; unless otherwise specified) Parameter Description Min Typ Max Unit Comments FCLK Clock Frequency − − 26 MHz TCLK Clock Period 38.4 − − ns NBIT Bits Number − 30/32 − bits Auto−detection 30−bit or 32−bit THIGH Clock High Time 13 − − ns TLOW Clock Low Time 13 − − ns TCSSETUP CS Set−up Time 5 − − ns 70% rising edge of CS to 30% rising edge of first clock cycle TCSHOLD CS Hold Time 5 − − ns 30% falling edge of last clock cycle to 70% falling edge of CS TDSETUP Data Set−up Time 4 − − ns Relative to 30% of CLK rising edge TDHOLD Data Hold Time 4 − − ns relative to 70% of CLK ris- ing edge TSUCC CS Low Time Between Successive Writes 38.4 − − ns 70% falling edge of CS to 70% rising edge of CS TSUCC CS Low Time Between Successive DAC Update Writes 1,500 − − ns Time between groups of DAC update reg [00000] & [00001] writes CCLK Input Capacitance − − 5 pF CLK pin CDATA Input Capacitance − − 8.3 pF DATA pin CCS Input Capacitance − − 5 pF CS pin CTRIG Input Capacitance − − 10 pF TRIG pin VIH Input Logic Level High 0.7 x VIO − VIO x 0.3 V DATA, CLK, CS VIL Input Logic Level Low −0.3 − 0.3 x VIO V DATA, CLK, CS IIH_DATA Input Current High −2 − 10 mA DATA IIL_DATA Input Current Low −2 − 1 mA DATA IIH_CLK,CS Input Current High −1 − 10 mA CLK, CS IIL_CLK,CS Input Current Low −1 − 1 mA CLK, CS VTP_TRIG Positive Going Threshold Volt- age 0.4 x VIO − 0.7 x VIO V TRIG VTN_TRIG Negative Going Threshold Volt- age 0.3 x VIO − 0.6 x VIO V TRIG VH_TRIG Hysteresis Voltage (VTP – VTN) 0.1 x VIO − 0.4 x VIO V TRIG IIH_TRIG TRIG Input Current High −2 − 10 mA TRIG=0.8 x VIO IIL_TRIG TRIG Input Current Low −2 − 1 mA TRIG=0.2 x VIO |
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