CM2009

http://onsemi.com

5

APPLICATION INFORMATION

Figure 1. Typical Application Connection Diagram

NOTES:

1. The CM2009 should be placed as close to the VGA or DVI−I connector as possible.

2. The ESD protection channels VIDEO_1, VIDEO_2, VIDEO_3 may be used interchangeably between the R, G, B

signals.

3. If differential video signal routing is used, the RED, BLUE, and GREEN signal lines should be terminated with

external 37.5

W resistors.

4. “VF” are external video filters for the RGB signals.

5. Supply bypass capacitors C1 and C2 must be placed immediately adjacent to the corresponding Vcc pins.

Connections to the Vcc pins and ground plane must be made with minimal length copper traces (preferably less than

5 mm) for best ESD protection.

6. The bypass capacitor for the BYP pin has been omitted in this diagram. This results in a reduction in the maximum

ESD withstand voltage at the DDC_OUT pins from

±8 kV to ±4 kV. If 8 kV ESD protection is required, a 0.2 mF

ceramic bypass capacitor should be connected between BYP and ground.

7. The SYNC buffers may be used interchangeably between HSYNC and VSYNC.

8. The EMI filters at the SYNC_OUT and DDC_OUT pins (C5 to C12, and Ferrite Beads FB1 to FB4) are for reference

only. The component values and filter configuration may be changed to suit the application.

9. The DDC level shifters DDC_IN, DDC_OUT, may be used interchangeably between DDCA_CLK and

DDCA_DATA.

10. R1, R2 are optional. They may be used, if required, to pull the DDC_CLK and DDC_DATA lines to VCC_5V when

no monitor is connected to the VGA connector. If used, it should be noted that “back current” may flow between the

DDC pins and VCC_5V via these resistors when VCC_5V is powered down.

11. For optimal ESD performance with the CM2009−02, an additional clamp device (such as the CMD PACDN042)

should be placed on HSYNC/VSYNC lines between the external matching resistor and the VGA connector.