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Z86C9524ASC Datasheet(PDF) 2 Page - Zilog, Inc. |
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Z86C9524ASC Datasheet(HTML) 2 Page - Zilog, Inc. |
2 / 18 page 2 Z86C95 DSP CPS DC-4067-13 GENERAL DESCRIPTION (Continued) 2. ICC2 at STOP Mode and DSP Pause will show a current of 1-2 mA, then will jump to 5-7 mA, and will settle at 3-4 mA. Settling time is about 10-15 seconds. 3. The zero error for the ADC at 25 °C is about 180 mV. Port 3 ALU Flags Register Pointer Register File 256 x 8-Bit Machine Timing and Instruction Control Vcc GND XTAL R//W /RESET Output Input /AS /DS SPI UART Three 16-Bit Counter/ Timers 32 ÷ 16 Divider 16 x 16 Multiplier Interrupt Control Digital Signal Processor Program Counter /WAIT Port 2 I/O (Bit Programmable) Address A15-A0* Address/Data 8 Program RAM DSP RAM Bank 1 ADC DSP RAM Bank 2 DAC 8 Channel Analog In Analog Out PWM PWM * In multiplexed mode, A7-A0 reflects the DSP address bus for emulation. AD7-AD0 Functional Block Diagram |
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