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Z89C00 Datasheet(PDF) 9 Page - Zilog, Inc. |
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Z89C00 Datasheet(HTML) 9 Page - Zilog, Inc. |
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9 / 28 page  Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR PRELIMINARY DC 4083-00 9 ZILOG S15-S12 are set/reset by the ALU after an operation. S11-S10 are set/reset by the user inputs. S6-S0 are control bits described elsewhere. S7 enables interrupts. S8, if 0 (reset), allows the hardware to overflow. If S8 is set, the hardware clamps at maximum positive or negative values instead of overflowing. If S9 is set and a multiply instruction is used, the shifter shifts the result three bits right with sign extension. PC is the Program Counter. When this register is assigned as a destination register, one NOP machine cycle is added automatically to adjust the pipeline timing. Figure 4. RAM, ROM, and Pointer Architecture 1. Register Indirect Pn:b n = 0-2, b = 0-1 The most commonly used method is a register indirect addressing method, where the RAM address is specified by one of the three RAM address pointers (n) for each bank (b). Each source/destination field in Figures 5 and 8 may be used by an indirect instruction to specify a register pointer and its modification after execution of the instruction. RAM Pointers P0:0 P1:0 P2:0 %37 RAM0 256 x 16-Bit @P1:0 %0321 %00 RAM1 256 x 16-Bit %0321 %00 Internal ROM 4K x 16-Bit %1234 %0000 %1000 %0321 @@P1:0 @D0:1 RAM Pointers P0:1 P1:1 P2:1 D0:0 %0321 D1:0 D2:0 D3:0 D0:1 D1:1 D2:1 D3:1 Data Pointers %37 %04 S4 / S3 = 01 The following Instructions load %1234 into the Accumulator: LD A,@@P1:0 LD A,@D0:1 %FF %FF D3 D2 D1 D0 D8 bn1 n0 RAM Pointer Register Operation RAM Bank Figure 5. Indirect Register RAM ADDRESSING The address of the RAM is specified in one of three ways (Figure 4): |
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