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54ACT109L Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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54ACT109L Datasheet(HTML) 1 Page - National Semiconductor (TI) |
1 / 8 page 54AC109 • 54ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description The ’AC/’ACT109 consists of two high-speed completely in- dependent transition clocked JK flip-flops. The clocking op- eration is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to ’AC/’ACT74 data sheet) by connecting the J and K inputs together. Asynchronous Inputs: LOW input to S D (Set) sets Q to HIGH level LOW input to C D (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on C D and SD makes both Q and Q HIGH Features n ICC reduced by 50% n Outputs source/sink 24 mA n ’ACT109 has TTL-compatible inputs n Standard Military Drawing (SMD) — ’AC109: 5962-89551 — ’ACT109: 5962-88534 Logic Symbol Pin Names Description J 1,J2,K1,K2 Data Inputs CP 1,CP2 Clock Pulse Inputs C D1,CD2 Direct Clear Inputs S D1,SD2 Direct Set Inputs Q 1,Q2,Q1,Q2 Outputs FACT® is a registered trademark of Fairchild Semiconductor Corporation. DS100267-1 DS100267-2 IEEE/IEC DS100267-7 August 1998 © 1998 National Semiconductor Corporation DS100267 www.national.com |
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