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54ACT109D Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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54ACT109D Datasheet(HTML) 2 Page - National Semiconductor (TI) |
2 / 8 page Connection Diagrams Truth Table (each half) Inputs Outputs S D C D CP J K QQ LH X X X H L HL X X X L H LL X X X H H HH N LL L H HH N H L Toggle HH N LH Q 0 Q 0 HH N HH H L HH L X X Q 0 Q 0 H = HIGH Voltage Level L = LOW Voltage Level N = LOW-to-HIGH Transition X = Immaterial Q0(Q0) = Previous Q0 (Q0) before LOW-to-HIGH Transition of Clock Logic Diagram (one half shown) Pin Assignment for DIP and Flatpak DS100267-3 Pin Assignment for LCC DS100267-4 DS100267-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 |
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