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TLV3501AQDBVRQ1 Datasheet(PDF) 11 Page - Texas Instruments |
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TLV3501AQDBVRQ1 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 22 page 0.1 F m 2.2 F m TLV3501-Q1 V REF V OUT V IN V = 5 V S R = 51 W 1 R = 10 kW 2 HYST (V ) R1 V 6 mV R1 R2 + ´ = + + TLV3501A-Q1 www.ti.com SBOS533B – SEPTEMBER 2010 – REVISED OCTOBER 2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Adding External Hysteresis The TLV3501A-Q1 device has a robust performance when used with a good layout. However, the comparator inputs have little noise immunity within the range of specified offset voltage (±5 mV). For slow moving or noisy input signals, the comparator output can cause an undesirable switch state as input signals move through the switching threshold. In such applications, the 6 mV of internal hysteresis of the TLV3501A-Q1 device might not be sufficient. In cases where greater noise immunity is desired, external hysteresis can be added by connecting a small amount of feedback to the positive. Figure 17 shows a typical topology used to introduce 25 mV of additional hysteresis, for a total of 31-mV hysteresis when operating from a single 5-V supply. Use Equation 1 to calculate the approximate total hysteresis. (1) The total hysteresis, VHYST, sets the value of the transition voltage required to switch the comparator output by enlarging the threshold region, thereby reducing sensitivity to noise. Figure 17. Adding Hysteresis to the TLV3501A-Q1 9.2 Typical Application 9.2.1 Relaxation Oscillator The TLV3501A-Q1 device can easily be configured as a simple and inexpensive relaxation oscillator. In Figure 18, the R2 network sets the trip threshold at 1/3 and 2/3 of the supply. Because this circuit is a high-speed circuit, the resistor values are rather low to minimize the effect of parasitic capacitance. The positive input alternates between 1/3 of V+ and 2/3 of V+ depending on whether the output is low or high. The time to charge (or discharge) is 0.69 × R1C. Therefore, the period is 1.38 × R1C. For 62 pF and 1 kΩ as shown in Figure 18, the output is calculated to be 10.9 MHz. An implementation of this circuit oscillated at 9.6 MHz. Parasitic capacitance and component tolerances explain the difference between theory and actual performance. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TLV3501A-Q1 |
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