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OPT8320 Datasheet(PDF) 7 Page - Texas Instruments |
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OPT8320 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 88 page  OPT8320 www.ti.com SBAS748 – DECEMBER 2015 Electrical Characteristics (continued) all specifications at TA = 25°C, VAVDDH = 3.3 V, VAVDD = 1.8 V, VVMIXH = 1.8 V, VDVDD = 1.8 V, VDVDDH = 3.3 V, VPVDD = 3.3 V, VSUB_BIAS = 0 V, integration duty cycle = 20%, system clock frequency = 24 MHz, VIOVDD = 1.8 V, modulation frequency = 48 MHz, quads = 4, sub-frames = 4, frame-rate = 30 FPS, and 850-nm illumination (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CMOS INPUTS/OUTPUTS VIH Input high-level threshold 0.7 × VCC(1) V VIL Input low-level threshold 0.3 × VCC(1) V VCC(1) – IOH = –2 mA 0.45 VOH Min Output high level V VCC(1) – IOH = –8 mA 0.5 IOL = 2 mA 0.35 VOL Max Output low level V IOL = 8 mA 0.65 Pins with pullup, pulldown resistor ±50 II Input pin leakage current µA Pins without pullup, pulldown ±10 resistor CI Input capacitance 5 pF IOH Max output current high level 10 mA IOL Max output current low level 10 mA (1) VCC is equal to IOVDD or DVDDH, based on the I/O bank listed in the table. 6.6 Timing Requirements MIN NOM MAX UNIT MCLK duty cycle 48% 52% MCLK frequency 24 MHz VD_IN pulse duration 2 × MCLK period RESET low pulse duration (reset) 100 ns 6.7 Switching Characteristics over operating free-air temperature range (unless otherwise noted); VDVDD = 1.8 V, VDVDDH = 3.3 V, and VIOVDD = 1.8 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARALLEL CMOS MODE (VIOVDD = 1.8 V) tSU Data setup time Data valid to zero crossing of CLKOUT 18.4 ns tH Data hold time Zero crossing of CLKOUT to data becoming invalid 21.1 ns tFALL, tRISE Data fall time, data rise time Rise time measured from 30% to 70% of IOVDD 1.75 ns tCLKRISE, Output clock rise time, Rise time measured from 30% to 70% of IOVDD 1.72 ns tCLKFALL output clock fall time PARALLEL CMOS MODE (VIOVDD = 3.3 V) tSU Data setup time Data valid to zero crossing of CLKOUT 18.3 ns tH Data hold time Zero crossing of CLKOUT to data becoming invalid 21.4 ns tFALL, tRISE Data fall time, data rise time Rise time measured from 30% to 70% of IOVDD 1.32 ns tCLKRISE, Output clock rise time, Rise time measured from 30% to 70% of IOVDD 1.39 ns tCLKFALL output clock fall time Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: OPT8320 |
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