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FAN3240TMX Datasheet(PDF) 3 Page - Fairchild Semiconductor |
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FAN3240TMX Datasheet(HTML) 3 Page - Fairchild Semiconductor |
3 / 19 page © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3240 • Rev. 1.0.2 3 Block Diagram OUT1 OUT2 IN1 IN2 VS EN 5VB GND 3 4 5 7 100 k Ω 100 k Ω 1 Timer / Filter / Protection TSD 2 Regulator Osc 8 Internal Bias EN EN Ref 6 UVLO Figure 3. Block Diagram Pin Definitions Pin Name Pin Description 1 EN Enable input for both channels. Pull pin LOW to inhibit operation of the drivers. This input has a precision threshold and comparator input stage. 2 5VB 5 V bypass pin for the internal 5 V regulator that provides power to the IC control circuitry. 3 IN1 Input to driver Channel 1. This input has TTL thresholds. 4 IN2 Input to driver Channel 2. This input has TTL thresholds. 5 OUT2 Relay drive output 2: Open-drain output. HIGH impedance unless required active input(s) are present and VS is above UVLO threshold. 6 GND Ground. Common ground reference for input and output circuits. 7 OUT1 Relay drive output 1: Open-drain output. HIGH impedance unless required active input(s) are present and VS is above UVLO threshold. 8 VS Supply voltage. Provides power to the device. Usually connected to the bias voltage of the relay being driven by the device. |
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Similar Description - FAN3240TMX |
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