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TAS5548DCA Datasheet(PDF) 9 Page - Texas Instruments

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Part # TAS5548DCA
Description  8-Channel HD Compatible Audio Processor
Download  116 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TAS5548DCA Datasheet(HTML) 9 Page - Texas Instruments

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TAS5548
www.ti.com
SLES270A – NOVEMBER 2012 – REVISED APRIL 2015
6.12
Mute Timing (MUTE)
Control signal parameters over recommended operating conditions (unless otherwise noted). See Figure 6
PARAMETER
MIN
TYP
MAX
UNIT
td(VOL)
Volume ramp time
Defined by rate setting(1)
ms
(1)
See Volume, Treble, and Bass Slew Rates Register (0xD0).
Note: No I2C commands during the volume ramp up/down.
6.13 Headphone Select (HP_SEL)
Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
tw(HP_SEL)
Pulse duration, HP_SEL active, see Figure 7
165
ms
Defined by rate
td(VOL)
Soft volume update time
ms
setting(1)
t(SW)
Switchover time
165
ms
(1)
See Volume, Treble, and Bass Slew Rates Register (0xD0).
6.14 Switching Characteristics - Clock Signals
PLL input parameters and external filter components over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
External PLL filter capacitors
SMD 0603 X7R
100
nF
External PLL filter capacitors
SMD 0603 X7R
10
nF
External PLL filter resistors
SMD 0603, metal film, 1%
200
External VR_PWM decoupling C14
SMD 0603 X7R
100
nF
12.28
TAS5548: XTAL Frequency
MHz
8
TAS5548: XTAL Frequency Tolerance at
±50
ppm
25°C
TAS5548: XTAL Load Capacitance
Follow XTAL Manufacturer specification
6.15
Switching Characteristics - Serial Audio Port
Serial audio port slave mode over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSCLKIN SCLK input frequency
CL = 30 pF
2.048
12.288
MHz
tsu1
Setup time, LRCLK to SCLK rising edge
10
ns
th1
Hold time, LRCLK from SCLK rising edge
10
ns
tsu2
Setup time, SDIN to SCLK rising edge
10
ns
th2
Hold time, SDIN from SCLK rising edge
10
ns
LRCLK frequency
32
48
192
kHz
SCLK
SCLK rising edges between LRCLK rising edges
64
64
edges
SDOUT delay with respect to SCLK output (load =
20
ns
30pF), see Figure 8
Copyright © 2012–2015, Texas Instruments Incorporated
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