TAS5612LA

SLAS847A – MAY 2012 – REVISED MARCH 2015

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Pin Functions (continued)

PIN

DESCRIPTION

NAME

NO.

OTW

17

O

Overtemperature warning, open drain, active low

OUT_A

39, 40

O

Output, half-bridge A

OUT_B

35

O

Output, half-bridge B

OUT_C

32

O

Output, half-bridge C

OUT_D

27, 28

O

Output, half-bridge D

PVDD_AB

36, 37, 38

P

PVDD supply for half-bridge A and B

PVDD_CD

29, 30, 31

P

PVDD supply for half-bridge C and D

RESET

4

I

Device reset Input; active low

VDD

2

P

Input power supply

PowerPAD™

–

P

Ground, connect to grounded heat sink

Mode Selection Pins

MODE PINS

PWM

OUTPUT

INPUT A

INPUT B

INPUT C

INPUT D

MODE

CONFIGURATION

M3

M2

M1

0

0

0

2N + 1

2 x BTL

PWMa

PWMb

PWMc

PWMd

AD mode

0

0

1

2 x BTL

PWMa

Unused

PWMc

Unused

AD mode

0

1

0

2N + 1

2 x BTL

PWMa

PWMb

PWMc

PWMd

BD mode

0

1

1

1 x BTL + 2 x SE

PWMa

Unused

PWMc

PWMd

AD mode

1

0

0

2N + 1

1 x PBTL

PWMa

PWMb

0

0

AD mode

1

0

0

1 x PBTL

PWMa

Unused

0

1

AD mode

1

0

0

2N + 1

1 x PBTL

PWMa

PWMb

1

0

BD mode

1

0

1

1N + 1

PWMa

PWMb

PWMc

PWMd

AD mode

(1)

The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.

(2)

Using 1N interface in BTL and PBTL mode results in increased DC offset on the output terminals.

(3)

The 4xSE mode can be used as 1xBTL + 2xSE configuration by feeding a 2N PWM signal to either INPUT_AB or INPUT_CD for

improved DC offset accuracy

4

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