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TUA6030 Datasheet(PDF) 21 Page - Infineon Technologies AG |
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TUA6030 Datasheet(HTML) 21 Page - Infineon Technologies AG |
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21 / 49 page  Functional Description 3 - 21 TUA6030, TUA6032 Wireless Components Specification, July 2001 By means of control bit CP the pump current can be switched between two val- ues by software. This programmability permits alteration of the control response of the PLL in the locked-in state. In this way different VCO gains can be com- pensated, for example. The software controlled ports P0 to P7 are general purpose open-collector out- puts. The test bits T2, T1, T0 =1, 0, 0 switch the test signals fdiv (divided input signal) and fref (i.e.4 MHz / 64) to P4 and P5 respectively. The lock detector resets the lock flag FL if the width of the charge pump current pulses is greater than the period of the crystal oscillator (i.e. 250 ns). Hence, if FL = 1, the maximum deviation of the input frequency from the programmed fre- quency is given by ∆f = ± I P ∗ (KVCO / fXTAL) ∗ (C1+C2) / (C1∗C2) where IP is the charge pump current, KVCO the VCO gain, fXtal the crystal oscil- lator frequency and C1, C2 the capacitances in the loop filter (Chapter 4). As the charge pump pulses at i.e. 62.5 kHz (= fref), it takes a maximum of 16 µs for FL to be reset after the loop has lost lock state. Once FL has been reset, it is set only if the charge pump pulse width is less than 250 ns for eight consecutive fref periods. Therefore it takes between 128 and 144 µs for FL to be set after the loop regains lock. 3.4.3 AGC The wide-band AGC stage detects the level of the IF output signal and gener- ates an AGC voltage for gain control of the tuner input transistors. The AGC take-over and the time constant are selectable by the I2C bus. 3.4.4 I2C-Bus Interface Data is exchanged between the processor and the PLL via the I2C bus. The clock is generated by the processor (input SCL). Pin SDA functions as an input or output depending on the direction of the data (open collector, external pull- up resistor). Both inputs have a hysteresis and a low-pass characteristic, which enhance the noise immunity of the I2C bus. The data from the processor pass through an I2C bus controller. Depending on their function the data are subsequently stored in registers. If the bus is free, both lines will be in the marking state (SDA, SCL are high). Each telegram begins with the start condition and ends with the stop condition. Start condition: SDA goes low, while SCL remains high. Stop condition: SDA goes high while |
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