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TAS5756M Datasheet(PDF) 11 Page - Texas Instruments |
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TAS5756M Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 104 page  TAS5756M www.ti.com SLAS988B – JUNE 2014 – REVISED AUGUST 2015 Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SERIAL AUDIO PORT Required LRCK/FS to tDLY 5 ns SCLK rising edge delay Allowable SCLK duty DSCLK 40% 60% cycle Supported input sample fS 8 192 kHz rates Supported SCLK fSCLK 32 64 fS (2) frequencies fSCLK SCLK frequency Either master mode or slave mode 24.576 MHz SPEAKER AMPLIFIER (ALL OUTPUT CONFIGURATIONS) SPK_GAIN/FREQ voltage < 3 V, see Adjustable Amplifier Gain and Switching 20 dBV Frequency Selection AV(SPK_AMP) Speaker amplifier gain SPK_GAIN/FREQ voltage > 3.3 V, see Adjustable Amplifier Gain and Switching 26 dBV Frequency Selection Typical variation of ΔAV(SPK_AMP) ±1 dBV speaker amplifier gain Switching frequency depends on voltage presented at SPK_GAIN/FREQ pin and the Switching frequency of fSPK_AMP clocking arrangement, including the incoming 176.4 768 kHz the speaker amplifier sample rate, see Adjustable Amplifier Gain and Switching Frequency Selection Injected Noise = 50 Hz to 60 Hz, 200 mVP-P, Power supply rejection KSVR Gain = 26 dBV, input audio signal = digital 60 dB ratio zero VPVDD = 24 V, I(SPK_OUT) = 500 mA, TJ = 25°C, Drain-to-source on includes PVDD/PGND pins, leadframe, 90 m Ω resistance of the rDS(on) bondwires and metallization layers. individual output MOSFETs VPVDD = 24 V, I(SPK_OUT) = 500 mA, TJ = 25°C 90 m Ω SPK_OUTxx Overcurrent OCETHRES 7.5 A Error Threshold Overtemperature Error OTETHRES 150 °C Threshold Time required to clear Overcurrent Error after OCECLRTIME 1.3 s error condition is removed. Time required to clear Overtemperature Error OTECLRTIME 1.3 s after error condition is removed. PVDD Overvoltage Error OVETHRES(PVDD) 27 V Threshold PVDD Undervoltage Error UVETHRES(PVDD) 4.5 V Threshold SPEAKER AMPLIFIER (STEREO BTL) Measured differentially with zero input data, SPK_GAIN/FREQ pin configured for 20 dBV 2 10 gain, VPVDD = 12 V |VOS| Amplifier offset voltage mV Measured differentially with zero input data, SPK_GAIN/FREQ pin configured for 26 dBV 6 15 gain, VPVDD = 24 V Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TAS5756M |
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