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C8051F972-A-GM Datasheet(PDF) 7 Page - Silicon Laboratories |
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C8051F972-A-GM Datasheet(HTML) 7 Page - Silicon Laboratories |
7 / 454 page C8051F97x Rev 1.0 7 27.7.Flash Error Reset....................................................................................................... 326 27.8.Software Reset .......................................................................................................... 326 27.9.Reset Sources Control Registers............................................................................... 327 27.10.Supply Monitor Control Registers ............................................................................ 328 28. Serial Peripheral Interface (SPI0) ................................................................................... 329 28.1.Signal Descriptions .................................................................................................... 330 28.1.1.Master Out, Slave In (MOSI) ............................................................................. 330 28.1.2.Master In, Slave Out (MISO) ............................................................................. 330 28.1.3.Serial Clock (SCK)............................................................................................. 330 28.1.4.Slave Select (NSS)............................................................................................ 330 28.2.SPI0 Master Mode Operation .................................................................................... 331 28.3.SPI0 Slave Mode Operation ...................................................................................... 333 28.4.SPI0 Interrupt Sources............................................................................................... 333 28.5.Serial Clock Phase and Polarity................................................................................. 333 28.6.SPI Special Function Registers ................................................................................. 335 28.7.SPI Control Registers ................................................................................................ 339 29. System Management Bus / I2C (SMBus0) ..................................................................... 343 29.1.Supporting Documents .............................................................................................. 344 29.2.SMBus Configuration ................................................................................................. 344 29.3.SMBus Operation....................................................................................................... 344 29.3.1.Transmitter vs. Receiver.................................................................................... 345 29.3.2.Arbitration .......................................................................................................... 345 29.3.3.Clock Low Extension ......................................................................................... 345 29.3.4.SCL Low Timeout .............................................................................................. 345 29.3.5.SCL High (SMBus Free) Timeout...................................................................... 346 29.4.Using the SMBus ....................................................................................................... 346 29.4.1.SMBus Configuration Register .......................................................................... 346 29.4.2.SMBus Pin Swap............................................................................................... 348 29.4.3.SMBus Timing Control....................................................................................... 348 29.4.4.SMB0CN Control Register................................................................................. 348 29.4.5.Hardware Slave Address Recognition............................................................... 350 29.4.6.Data Register..................................................................................................... 350 29.5.SMBus Transfer Modes ............................................................................................. 351 29.5.1.Write Sequence (Master)................................................................................... 351 29.5.2.Read Sequence (Master) .................................................................................. 352 29.5.3.Write Sequence (Slave)..................................................................................... 353 29.5.4.Read Sequence (Slave) .................................................................................... 354 29.6.SMBus Status Decoding ............................................................................................ 354 29.7.I2C / SMBus Control Registers .................................................................................. 359 30. I2C Slave ........................................................................................................................... 365 30.1.Supporting Documents .............................................................................................. 366 30.2.The I2C Configuration................................................................................................ 366 30.3.I2CSLAVE0 Operation ............................................................................................... 366 30.3.1.Transmitter vs. Receiver.................................................................................... 367 30.3.2.Clock Stretching ................................................................................................ 367 30.3.3.SCL Low Timeout .............................................................................................. 368 |
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