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C8051F901-D-GU Datasheet(PDF) 7 Page - Silicon Laboratories |
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C8051F901-D-GU Datasheet(HTML) 7 Page - Silicon Laboratories |
7 / 335 page C8051F91x-C8051F90x Rev. 1.3 7 22.2.SMBus Configuration...................................................................................... 231 22.3.SMBus Operation ........................................................................................... 232 22.3.1.Transmitter Vs. Receiver........................................................................ 232 22.3.2.Arbitration............................................................................................... 233 22.3.3.Clock Low Extension.............................................................................. 233 22.3.4.SCL Low Timeout................................................................................... 233 22.3.5.SCL High (SMBus Free) Timeout .......................................................... 233 22.4.Using the SMBus............................................................................................ 234 22.4.1.SMBus Configuration Register............................................................... 235 22.4.2.SMB0CN Control Register ..................................................................... 238 22.4.3.Hardware Slave Address Recognition ................................................... 241 22.4.4.Data Register ......................................................................................... 243 22.5.SMBus Transfer Modes.................................................................................. 244 22.5.1.Write Sequence (Master) ....................................................................... 244 22.5.2.Read Sequence (Master) ....................................................................... 245 22.5.3.Write Sequence (Slave) ......................................................................... 246 22.5.4.Read Sequence (Slave) ......................................................................... 247 22.6.SMBus Status Decoding................................................................................. 247 23. UART0.................................................................................................................... 252 23.1.Enhanced Baud Rate Generation................................................................... 253 23.2.Operational Modes ......................................................................................... 254 23.2.1.8-Bit UART ............................................................................................. 254 23.2.2.9-Bit UART ............................................................................................. 255 23.3.Multiprocessor Communications .................................................................... 255 24. Enhanced Serial Peripheral Interface (SPI0 and SPI1)...................................... 260 24.1.Signal Descriptions......................................................................................... 261 24.1.1.Master Out, Slave In (MOSI).................................................................. 261 24.1.2.Master In, Slave Out (MISO).................................................................. 261 24.1.3.Serial Clock (SCK) ................................................................................. 261 24.1.4.Slave Select (NSS) ................................................................................ 261 24.2.SPI Master Mode Operation ........................................................................... 262 24.3.SPI Slave Mode Operation ............................................................................. 264 24.4.SPI Interrupt Sources ..................................................................................... 264 24.5.Serial Clock Phase and Polarity ..................................................................... 265 24.6.SPI Special Function Registers ...................................................................... 267 25. Timers.................................................................................................................... 274 25.1.Timer 0 and Timer 1 ....................................................................................... 276 25.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 276 25.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 277 25.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 278 25.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 279 25.2.Timer 2 .......................................................................................................... 284 25.2.1.16-bit Timer with Auto-Reload................................................................ 284 25.2.2.8-bit Timers with Auto-Reload................................................................ 285 25.2.3.Comparator 0/SmaRTClock Capture Mode ........................................... 286 |
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