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C8051F860-C-GS Datasheet(PDF) 10 Page - Silicon Laboratories |
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C8051F860-C-GS Datasheet(HTML) 10 Page - Silicon Laboratories |
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10 / 328 page  9 Rev. 1.0 Digital Core Supply Current (–Ix Devices, -40°C to +125°C) Normal Mode—Full speed with code executing from flash IDD FSYSCLK = 24.5 MHz 2 — 4.45 5.25 mA FSYSCLK = 1.53 MHz 2 — 915 1600 μA FSYSCLK = 80 kHz 3, T A = 25 °C — 250 290 μA FSYSCLK = 80 kHz 3 — 250 725 μA Idle Mode—Core halted with peripherals running IDD FSYSCLK = 24.5 MHz 2 — 2.05 2.6 mA FSYSCLK = 1.53 MHz 2 — 550 1000 μA FSYSCLK = 80 kHz 3, T A = 25 °C — 125 130 μA FSYSCLK = 80 kHz 3 — 125 550 μA Stop Mode—Core halted and all clocks stopped, Supply monitor off. IDD Internal LDO ON, TA = 25 °C — 105 120 μA Internal LDO ON — 105 270 μA Internal LDO OFF — 0.2 — μA Analog Peripheral Supply Currents (Both –Gx and –Ix Devices) High-Frequency Oscillator IHFOSC Operating at 24.5 MHz, TA = 25 °C — 155 — µA Low-Frequency Oscillator ILFOSC Operating at 80 kHz, TA = 25 °C — 3.5 — µA ADC0 Always-on4 IADC 800 ksps, 10-bit conversions or 200 ksps, 12-bit conversions Normal bias settings VDD = 3.0 V — 845 1200 µA 250 ksps, 10-bit conversions or 62.5 ksps 12-bit conversions Low power bias settings VDD = 3.0 V — 425 580 µA ADC0 Burst Mode, 10-bit sin- gle conversions, external ref- erence IADC 200 ksps, VDD = 3.0 V — 370 — µA 100 ksps, VDD = 3.0 V — 185 — µA 10 ksps, VDD = 3.0 V — 19 — µA Table 1.2. Power Consumption (Continued) Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Currents are additive. For example, where IDD is specified and the mode is not mutually exclusive, enabling the functions increases supply current by the specified amount. 2. Includes supply current from internal regulator, supply monitor, and High Frequency Oscillator. 3. Includes supply current from internal regulator, supply monitor, and Low Frequency Oscillator. 4. ADC0 always-on power excludes internal reference supply current. 5. The internal reference is enabled as-needed when operating the ADC in burst mode to save power. |
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