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C8051F968-B-GQ Datasheet(PDF) 3 Page - Silicon Laboratories |
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C8051F968-B-GQ Datasheet(HTML) 3 Page - Silicon Laboratories |
3 / 492 page Rev. 1.0 3 C8051F96x 5.10. External Voltage Reference........................................................................... 101 5.11. Internal Voltage Reference............................................................................ 101 5.12. Analog Ground Reference............................................................................. 101 5.13. Temperature Sensor Enable ......................................................................... 101 5.14. Voltage Reference Electrical Specifications .................................................. 102 6. Programmable Current Reference (IREF0).......................................................... 103 6.1. PWM Enhanced Mode..................................................................................... 103 6.2. IREF0 Specifications ....................................................................................... 104 7. Comparators........................................................................................................... 105 7.1. Comparator Inputs........................................................................................... 105 7.2. Comparator Outputs ........................................................................................ 106 7.3. Comparator Response Time ........................................................................... 107 7.4. Comparator Hysterisis ..................................................................................... 107 7.5. Comparator Register Descriptions .................................................................. 108 7.6. Comparator0 and Comparator1 Analog Multiplexers ...................................... 112 8. CIP-51 Microcontroller........................................................................................... 115 8.1. Instruction Set.................................................................................................. 116 8.1.1. Instruction and CPU Timing .................................................................... 116 8.2. CIP-51 Register Descriptions .......................................................................... 121 9. Memory Organization ............................................................................................ 124 9.1. Program Memory............................................................................................. 124 9.1.1. MOVX Instruction and Program Memory ................................................ 127 9.2. Data Memory ................................................................................................... 127 9.2.1. Internal RAM ........................................................................................... 127 9.2.2. External RAM .......................................................................................... 128 10. External Data Memory Interface and On-Chip XRAM ....................................... 129 10.1. Accessing XRAM........................................................................................... 129 10.1.1. 16-Bit MOVX Example .......................................................................... 129 10.1.2. 8-Bit MOVX Example ............................................................................ 129 10.2. Configuring the External Memory Interface ................................................... 130 10.3. Port Configuration.......................................................................................... 130 10.4. Multiplexed and Non-multiplexed Selection................................................... 134 10.4.1. Multiplexed Configuration...................................................................... 134 10.4.2. Non-multiplexed Configuration.............................................................. 134 10.5. Memory Mode Selection................................................................................ 135 10.5.1. Internal XRAM Only .............................................................................. 136 10.5.2. Split Mode without Bank Select............................................................. 136 10.5.3. Split Mode with Bank Select.................................................................. 136 10.5.4. External Only......................................................................................... 136 10.6. Timing .......................................................................................................... 137 10.6.1. Non-Multiplexed Mode .......................................................................... 139 10.6.2. Multiplexed Mode .................................................................................. 142 11. Direct Memory Access (DMA0)........................................................................... 146 11.1. DMA0 Architecture ........................................................................................ 147 11.2. DMA0 Arbitration ........................................................................................... 148 |
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