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C8051F997-C-GU Datasheet(PDF) 8 Page - Silicon Laboratories |
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C8051F997-C-GU Datasheet(HTML) 8 Page - Silicon Laboratories |
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8 / 325 page  C8051F99x-C8051F98x 8 Rev. 1.2 List of Figures Figure 1.1. C8051F980 Block Diagram .................................................................... 18 Figure 1.2. C8051F981 Block Diagram .................................................................... 18 Figure 1.3. C8051F982 Block Diagram .................................................................... 19 Figure 1.4. C8051F983 Block Diagram .................................................................... 19 Figure 1.5. C8051F985 Block Diagram .................................................................... 20 Figure 1.6. C8051F986 Block Diagram .................................................................... 20 Figure 1.7. C8051F987 Block Diagram .................................................................... 21 Figure 1.8. C8051F988 Block Diagram .................................................................... 21 Figure 1.9. C8051F989 Block Diagram .................................................................... 22 Figure 1.10. C8051F990 Block Diagram .................................................................. 22 Figure 1.11. C8051F991 Block Diagram .................................................................. 23 Figure 1.12. C8051F996 Block Diagram .................................................................. 23 Figure 1.13. C8051F997 Block Diagram .................................................................. 24 Figure 1.14. Port I/O Functional Block Diagram ....................................................... 26 Figure 1.15. PCA Block Diagram.............................................................................. 27 Figure 1.16. ADC0 Functional Block Diagram.......................................................... 28 Figure 1.17. ADC0 Multiplexer Block Diagram ......................................................... 29 Figure 1.18. Comparator 0 Functional Block Diagram ............................................. 30 Figure 3.1. QFN-20 Pinout Diagram (Top View) ...................................................... 35 Figure 3.2. QFN-24 Pinout Diagram (Top View) ...................................................... 36 Figure 3.3. QSOP-24 Pinout Diagram (Top View).................................................... 37 Figure 3.4. QFN-20 Package Marking Diagram ....................................................... 38 Figure 3.5. QFN-24 Package Marking Diagram ....................................................... 38 Figure 3.6. QSOP-24 Package Marking Diagram .................................................... 39 Figure 3.7. QFN-20 Package Drawing ..................................................................... 40 Figure 3.8. Typical QFN-20 Landing Diagram.......................................................... 41 Figure 3.9. QFN-24 Package Drawing ..................................................................... 43 Figure 3.10. Typical QFN-24 Landing Diagram........................................................ 44 Figure 3.11. QSOP-24 Package Diagram ................................................................ 46 Figure 3.12. QSOP-24 Landing Diagram ................................................................. 47 Figure 4.1. Active Mode Current (External CMOS Clock) ........................................ 52 Figure 4.2. Idle Mode Current (External CMOS Clock) ............................................ 53 Figure 4.3. Typical VOH Curves, 1.8–3.6 V ............................................................. 55 Figure 4.4. Typical VOL Curves, 1.8–3.6 V .............................................................. 56 Figure 5.1. ADC0 Functional Block Diagram............................................................ 66 Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0).... 69 Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4 ................... 70 Figure 5.4. ADC0 Equivalent Input Circuits .............................................................. 71 Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data ... 82 Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data...... 82 Figure 5.7. ADC0 Multiplexer Block Diagram ........................................................... 83 Figure 5.8. Temperature Sensor Transfer Function ................................................. 85 Figure 5.9. Temperature Sensor Error with 1-Point Calibration (VREF = 1.65 V) ..... 86 |
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