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EFM8BB3 Datasheet(PDF) 9 Page - Silicon Laboratories |
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EFM8BB3 Datasheet(HTML) 9 Page - Silicon Laboratories |
9 / 70 page Universal Asynchronous Receiver/Transmitter (UART1) UART1 is an asynchronous, full duplex serial port offering a variety of data formatting options. A dedicated baud rate generator with a 16-bit timer and selectable prescaler is included, which can generate a wide range of baud rates. A received data FIFO allows UART1 to receive multiple bytes before data is lost and an overflow occurs. UART1 provides the following features: • Asynchronous transmissions and receptions • Dedicated baud rate generator supports baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive) • 5, 6, 7, 8, or 9 bit data • Automatic start and stop generation • Automatic parity generation and checking • Single-byte buffer on transmit and receive • Auto-baud detection • LIN break and sync field detection • CTS / RTS hardware flow control Serial Peripheral Interface (SPI0) The serial peripheral interface (SPI) module provides access to a flexible, full-duplex synchronous serial bus. The SPI can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select the SPI in slave mode, or to disable master mode operation in a multi-master environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be configured as a firmware-controlled chip-select output in master mode, or disabled to reduce the number of pins required. Additional general purpose port I/O pins can be used to select multiple slave devices in master mode. • Supports 3- or 4-wire master or slave modes • Supports external clock frequencies up to 12 Mbps in master or slave mode • Support for all clock phase and polarity modes • 8-bit programmable clock rate (master) • Programmable receive timeout (slave) • Two byte FIFO on transmit and receive • Can operate in suspend or snooze modes and wake the CPU on reception of a byte • Support for multiple masters on the same data lines System Management Bus / I2C (SMB0) The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specifica- tion, version 1.1, and compatible with the I2C serial bus. The SMBus module includes the following features: • Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds • Support for master, slave, and multi-master modes • Hardware synchronization and arbitration for multi-master mode • Clock low extending (clock stretching) to interface with faster masters • Hardware support for 7-bit slave and general call address recognition • Firmware support for 10-bit slave address decoding • Ability to inhibit all slave states • Programmable data setup/hold times • Transmit and receive buffers to help increase throughput in faster applications EFM8BB3 Data Sheet System Overview silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.2 | 8 |
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