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TPA3110D2QPWPRQ1 Datasheet(PDF) 4 Page - Texas Instruments |
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TPA3110D2QPWPRQ1 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 36 page TPA3110D2-Q1 SLOS794B – SEPTEMBER 2012 – REVISED SEPTEMBER 2015 www.ti.com Pin Functions (continued) PIN TYPE DESCRIPTION NO. NAME Power supply for left channel H-bridge. Right channel and left channel power supply inputs 27 PVCCL P are connect internally. Power supply for left channel H-bridge. Right channel and left channel power supply inputs 28 PVCCL P are connect internally. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VCC Supply voltage AVCC, PVCC –0.3 30 V –0.3 VCC + 0.3 V SD, GAIN0, GAIN1, PBTL, FAULT(2) < 10 V/ms Interface pin VI voltage PLIMIT –0.3 GVDD + 0.3 V RINN, RINP, LINN, LINP –0.3 6.3 V BTL: PVCC > 15 V 4.8 Minimum load RL BTL: PVCC ≤ 15 V 3.2 resistance PBTL 3.2 Continuous total power dissipation See the Thermal Information Table TA Operating free-air temperature –40 125 °C TJ Operating junction temperature(3) –40 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100-k Ω resistor in series with the pins, per application note SLUA626. (3) The TPA3110D2-Q1 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection shutdown. See TI Technical Brief SLMA002 for more information about using the TSSOP thermal pad. 6.2 ESD Ratings VALUE UNIT Human-body model (HBM), per AEC Q100-002(1) ±4000 V(ESD) Electrostatic discharge Charged-device model (CDM), per AEC Q100-011 ±250 V Machine Model (MM) per JESD22-A115 ±200 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage PVCC, AVCC 8 26 V VIH High-level input voltage SD, GAIN0, GAIN1, PBTL 2 V VIL Low-level input voltage SD, GAIN0, GAIN1, PBTL 0.8 V VOL Low-level output voltage FAULT, RPULL-UP = 100k, VCC = 26 V 0.8 V IIH High-level input current SD, GAIN0, GAIN1, PBTL, VI = 2 V, VCC = 18 V 50 µA IIL Low-level input current SD, GAIN0, GAIN1, PBTL, VI = 0.8 V, VCC = 18 V 5 µA TA Operating free-air temperature –40 125 °C 4 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 |
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