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CP2114 Datasheet(PDF) 9 Page - Silicon Laboratories

Part # CP2114
Description  INTERFACE SPECIFICATION
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

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AN434
Rev. 0.4
9
4. Device Configuration Reports
4.1. Set Reset Device
Report ID: 0x40
Direction: Control Out
Set Reset Device is used to restart the device from the USB host. The device will re-enumerate on the USB bus
and all UART configuration settings are reset to their default values.
For certain operating systems such as Windows, initiating a device reset and re-enumerating will make the device's
handle stale. The user application is responsible for handling this "surprise disconnect" event. See AN433: CP2110
HID-to-UART API Specification for more information regarding surprise disconnects.
4.2. Get/Set UART Enable
Report ID: 0x41
Direction: Control In/Out
Get UART Enable returns the Enable status of the UART. The UART is disabled by default.
Set UART Enable checks the FlushBuffers programmed parameter and purges the FIFOs depending on the
parameter Enable or Disable, which are treated as Open and Close respectively.
4.3. Get UART Status
Report ID: 0x42
Direction: Control In
TX FIFO is the number of bytes left for the device transfer to the UART-based device. The transmit FIFO buffer can
hold up to 480 bytes. The value returned is a two-byte, unsigned integer.
RX FIFO is the number of bytes left for the device to transfer to the USB host. The receive FIFO buffer can hold up
to 480 bytes. The value returned is a two-byte, unsigned integer.
Error Status indicates if a Parity error (mask 0x01) or Overrun error (0x02) has occurred since the last time Error
Status was read by the user. Reading Error Status clears the errors.
Break Status indicates if a line break is currently in progress.
Name
Offset
Size
Value
Description
Reset Type
1
1
0x00
Reset with re-enumeration
Name
Offset
Size
Value
Description
UART Enable
1
1
0x00
0x01
UART disabled
UART enabled
Name
Offset
Size
Value
Description
TX FIFO
1
2
See below
Number of bytes in Transmit FIFO
RX FIFO
3
2
See below
Number of bytes in the Receive FIFO
Error Status
5
1
See below
Parity and Overrun errors
Break Status
6
1
0x00
0x01
Line break is not active
Line break is active


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