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CP2108-B01-GM Datasheet(PDF) 6 Page - Silicon Laboratories |
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CP2108-B01-GM Datasheet(HTML) 6 Page - Silicon Laboratories |
6 / 30 page CP2108 6 Rev. 1.1 Table 3. UART, GPIO, and Suspend I/O VDD= 3.0 to 3.6 V, VIO=1.8 V to VDD, VIOHD = 2.7 V to 6.0 V, –40 to +85 °C unless otherwise specified. Parameter Symbol Test Condition Min Typ Max Unit Output High Voltage (All pins except High Drive UART 3 pins 1–6) VOH VIO –0.7 — — V Output High Voltage (High Drive UART 3 pins 1–6) VIOHD –0.7 — — V Output Low Voltage (All pins except High Drive pins 1–6) VOL Low Drive IOL = 3 mA —— 0.6 V Output Low Voltage (High Drive pins 1–6) High Drive IOL = 12.5 mA 0.6 V Input High Voltage VIH 3.0 < VIO < 3.6 VIO –0.6 — — V Input Low Voltage VIL —— 0.6 V Weak Pull-up Current (VIN = 0 V) IPU VIO = 3.6 V –30 –20 –10 µA Weak Pull-up Current UART 3 (pins 1–6) IPU VIOHD = 2.7 V –15 –10 –5 µA VIOHD = 6.0 V –30 –20 –10 µA Table 4. GPIO Output Specifications –40 to +85°C unless otherwise specified. Parameter Symbol Test Condition Min Typ Max Unit RS-485 Active Time After Stop Bit tACTIVE —1 — bit time* TX Toggle Rate fTXTOG —15 — Hz RX Toggle Rate fRXTOG —15 — Hz Clock Output Rate fCLOCK 78k — 20M Hz *Note: Bit-time is calculated as 1 / baud rate. Table 5. Reset –40 to +85 °C unless otherwise specified. Parameter Symbol Test Condition Min Typ Max Unit Power-On Reset (POR) Threshold VPOR Rising Voltage on VDD —1.4 — V Falling Voltage on VDD 0.8 1 1.3 V VDD Ramp Time tRMP Time to VDD > 3.0 V 10 — 3000 µs RESET Input High Voltage VIHRESET 3.0 < VIO < 3.6 VIO – 0.6 — — V RESET Input Low Voltage VILRESET —— 0.6 V RESET Low Time to Generate Reset tRSTL 50 — — ns |
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