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SI513 Datasheet(PDF) 6 Page - Silicon Laboratories |
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SI513 Datasheet(HTML) 6 Page - Silicon Laboratories |
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6 / 20 page  Si512/513 6 Rev. 1.0 Table 3. Output Clock Levels and Symmetry VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC Parameter Symbol Test Condition Min Typ Max Units CMOS Output Logic High VOH 0.85 x VDD —— V CMOS Output Logic Low VOL — — 0.15 x VDD V CMOS Output Logic High Drive IOH 3.3 V –8 — — mA 2.5 V –6 — — mA 1.8 V –4 — — mA CMOS Output Logic Low Drive IOL 3.3 V 8 — — mA 2.5 V 6 — — mA 1.8 V 4 — — mA CMOS Output Rise/Fall Time (20 to 80% VDD) TR/TF 0.1 to 125 MHz, CL = 15 pF —0.8 1.2 ns 0.1 to 212.5 MHz, CL = no load —0.6 0.9 ns LVPECL/HCSL Output Rise/Fall Time (20 to 80% VDD) TR/TF —— 565 ps LVDS Output Rise/Fall Time (20 to 80% VDD) TR/TF —— 800 ps LVPECL Output Common Mode VOC 50 to VDD – 2 V, single-ended —VDD – 1.4 V —V LVPECL Output Swing VO 50 to VDD – 2 V, single-ended 0.55 0.8 0.90 VPPSE LVDS Output Common Mode VOC 100 line-line, VDD = 3.3/2.5 V 1.13 1.23 1.33 V 100 line-line, VDD = 1.8 V 0.83 0.92 1.00 V LVDS Output Swing VO Single-ended, 100 differential termination 0.25 0.35 0.45 VPPSE HCSL Output Common Mode VOC 50 to ground 0.35 0.38 0.42 V HCSL Output Swing VO Single-ended 0.58 0.73 0.85 VPPSE Duty Cycle DC All Output Formats 48 50 52 % |
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