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HV2761 Datasheet(PDF) 6 Page - Supertex, Inc |
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HV2761 Datasheet(HTML) 6 Page - Supertex, Inc |
6 / 8 page 6 HV2761 Supertex inc. www.supertex.com Doc.# DSFP-HV2761 NR010913 Logic Timing Waveforms Truth Table DATA IN DIN LE CLOCK DATA OUT DOUT OFF V OUT (typ) ON CLR 50% 50% 50% 50% t WLE t SD 50% 50% t SU t h t OFF 50% t DO t ON t WCL D N + 1 D N D N - 1 50% 50% 90% 10% D0 D1 ... D15 D16 ... D23 LE CLR SW0 SW1 ... SW15 SW16 ... SW23 L - ... - - ... - L L OFF - ... - - ... - H - - - - L L ON - - - - - L - - - L L - OFF - - - - H - - - L L - ON - - - - - - - - L L - - - - - - - - - - L L - - - - - - - L - - L L - - OFF - - - - H - - L L - - ON - - - - - L - L L - - - OFF - - - - H - L L - - - ON - - - - - - L L - - - - - - - - - - L L - - - - - - - - - - L L - - - - - - - - - - L L - - - - - - - - - L L L - - - - OFF - - - - H L L - - - - ON X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X H ALL SWITCHES OFF Notes: 1. The 24 switches operate independently. 2. Serial data is clocked in on the L to H transition of the CLK. 3. All 24 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low the shift registers data flow through the latch. 4. DOUT is high when data in the register 23 is high. 5. Shift registers clocking has no effect on the switch states if LE is high. 6. The CLR clear input overrides all other inputs. |
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