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LMK03318RHSR Datasheet(PDF) 7 Page - Texas Instruments |
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LMK03318RHSR Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 136 page  LMK03318 www.ti.com SNAS669A – SEPTEMBER 2015 – REVISED DECEMBER 2015 8.5 Thermal Information LMK0331 8 THERMAL METRIC(1) CONDITION UNIT RHA QFN-48 Junction-to-ambient thermal RθJA 10-layer 200 mm x 250 mm board, 36 thermal vias, Airflow = 0 LFM 10 °C/W resistance Junction-to-board characterization ψJB 10-layer 200 mm x 250 mm board, 36 thermal vias, Airflow = 0 LFM 2.8 °C/W parameter (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 8.6 Electrical Characteristics - Power Supply VDD_IN, VDD_PLL, VDD_LDO, VDD_DIG = 3.3 V ± 5%, VDDO_x = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40°C to +85°C (1) (2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Primary input (differential or single ended) - active 10 Secondary input (differential or single ended) - active 10 Secondary input (XO) - active 11 Core current consumption, lDD mA per block PLL doubler - active 4 PLL block – active 110 Control block 53 Output channel (MUX and Divider only) – active 46 AC-LVDS driver (one pair) 10 AC-coupled to 100 Ω differential AC-LVPECL driver (one pair), AC-coupled to 100 Ω 18 differential AC-CML driver (one pair), AC-coupled to 100 Ω Output current 16 IDDO differential mA consumption, per block HCSL driver (one pair) 25 50 Ω to GND 1.8-V LVCMOS driver (two outputs), 100 MHz, 5-pF 10 load(2) 3.3-V LVCMOS driver on STATUS0, STATUS1, 100 21 MHz, 5-pF load(2) IDD_IN Inputs: 48 65 mA - PRI input enabled, set to LVDS mode IDD_PLL 128 158 mA - SEC input enabled, set to crystal mode IDD_LDO 15 30 mA - Input MUX set to auto select - Reference clock is 25 MHz IDD_DIG 19 38 mA - R dividers set to 1 IDDO_01 85 105 mA PLL: - M divider = 1 IDDO_23 85 105 mA - Doubler enabled IDDO_4 58 75 mA - ICP = 6.4 mA Current consumption, per - Loop bandwidth = 400 kHz IDDO_5 58 75 mA supply pin - VCO Frequency = 5 GHz IDDO_6 58 75 mA - Feedback divider = 100 - Post divider = 8 Outputs: - OUT[0-7] = 156.25 MHz LVPECL - STATUS1: Loss of lock PLL IDDO_7 58 75 mA - STATUS0: Loss of secondary reference Power Supplies: - VDD_IN, VDD_PLL, VDD_LDO, VDD_DIG = 3.3 V - VDDO_xx = 3.3 V IDD-PD Total device, LMK03318 Power down (PDN = 0) 30 50 mA (1) Refer to Parameter Measurement Information for relevant test conditions. (2) PTOTAL = PDC + PAC, where: PDC = 3.4 mA typical. PAC = C × V 2 × f OUT. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LMK03318 |
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