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LMK03318RHSR Datasheet(PDF) 9 Page - Texas Instruments |
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LMK03318RHSR Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 136 page  LMK03318 www.ti.com SNAS669A – SEPTEMBER 2015 – REVISED DECEMBER 2015 8.8 Non-Pullable Crystal Characteristics (SECREF_P, SECREF_N) VDD_IN, VDD_PLL, VDD_LDO, VDD_DIG = 3.3 V ± 5%, VDDO_x = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40°C to +85°C (1) (2) (3) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fXTAL Crystal frequency Fundamental mode 10 52 MHz ESR Equivalent series resistance fXTAL = 10 MHz to 16 MHz 60 Ω fXTAL = 16 MHz to 30 MHz 50 fXTAL = 30 MHz to 52 MHz 30 PXTAL Crystal maximum drive level 300 uW CXO On-Chip XO input capacitance Single-ended, each pin referenced to 14 24 pF at Xi and Xo GND Con-chip-5p-load On-chip tunable capacitor Frequency accuracy of crystal over 450 fF variation over VT across temperature, aging and initial accuracy crystal load of 5 pF < ± 25 ppm. Con-chip-12p-load On-chip tunable capacitor Frequency accuracy of crystal over 1.5 pF variation over VT across temperature, aging and initial accuracy crystal load of 12 pF < ± 25 ppm. (1) Parameter is specified by characterization and is not tested in production. (2) Using a crystal with higher ESR can degrade XO phase noise and may impact crystal start-up. (3) Verified with crystals specified for a load capacitance of CL = 9 pF. PCB stray capacitance was measured to be 1 pF. Crystal tested: 25 MHz TXC (part number: 7M25072001). 8.9 Clock Input Characteristics (PRIREF_P/PRIREF_N, SECREF_P/SECREF_N) VDD_IN, VDD_PLL, VDD_LDO, VDD_DIG = 3.3 V ± 5%, VDDO_x = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40°C to 85°C (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fCLK Input frequency range 1 300 MHz VIH (2) LVCMOS input high voltage PRI_REF 1.4 VDD_IN V VIH (2) LVCMOS input high voltage SEC_REF 1.4 2.6 V VIL (2) LVCMOS input low voltage 0 0.5 V VID,DIFF,PP Input voltage swing, Differential input (where VCLK – VnCLK = |VID| × 2) 0.2 2 V differential peak-peak VICM Input common mode voltage Differential input 0.1 2 V dV/dt(3) Input edge slew rate (20% to Differential input, peak-peak 0.5 V/ns 80%) Single-ended input, non-driven input tied to GND 0.5 V/ns IDC(3) Input clock duty cycle 40% 60% IIN Input leakage current –100 100 µA CIN Input capacitance Single-ended, each pin 2 pF (1) Refer to Parameter Measurement Information for relevant test conditions. (2) Slew-rate-detect circuitry must be used when VIH > 1.7 V and VIL < 0.2 V. VIH/VIL detect circuitry must be used when VIH > 1.5 V and VIL < 0.4 V. Refer to REFDETCTL Register; R25 for relevant register information. (3) Ensured by characterization. 8.10 VCO Characteristics VDD_IN, VDD_PLL, VDD_LDO, VDD_DIG = 3.3 V ± 5%, VDDO_x = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40°C to +85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fVCO Frequency range 4.8 5.4 GHz KVCO VCO Gain 55 MHz/V Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LMK03318 |
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