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LMK03318RHST Datasheet(PDF) 6 Page - Texas Instruments |
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LMK03318RHST Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 136 page  LMK03318 SNAS669A – SEPTEMBER 2015 – REVISED DECEMBER 2015 www.ti.com 8 Specifications 8.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply voltage for input, synthesizer, control, and output blocks, VDD_IN, VDD_PLL, VDD_LDO, –0.3 3.6 V VDD_DIG, VDDO_x Input voltage range, clock and logic inputs, VIN –0.3 VDD +0.3 V Output voltage range for clock and logic outputs, VOUT –0.3 VDD + 0.3 V Junction temperature, TJ 150 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute mAximum-rated conditions for extended periods may affect device reliability. 8.2 ESD Ratings VALUE UNIT Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ± 2000 V(ESD) Electrostatic discharge V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ± 500 (1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. 8.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply voltage for input, analog, control blocks, VDD_IN, VDD_PLL, VDD_LDO, VDD_DIG 3.135 3.3 3.465 V 1.8 Supply voltage for output drivers (Differential, LVCMOS), VDDO_x 1.7 2.5 3.465 V 3.3 Ambient temperature, TA -40 25 85 °C Junction temperature, TJ 125 °C Maximum VDD power-up ramp, dVDD/dt 0.1 100 ms EEPROM number of writes, WR 100 8.4 Thermal Information LMK03318 (2) (3) (4) RHA THERMAL METRIC(1) UNIT QFN-48 Airflow (LFM) 0 Airflow (LFM) 200 Airflow (LFM) 400 RθJA Junction-to-ambient thermal resistance 26.47 16.4 14.62 RθJC(top) Junction-to-case (top) thermal resistance 16.57 n/a n/a RθJB Junction-to-board thermal resistance 6.84 n/a n/a °C/W ψJT Junction-to-top characterization parameter 0.23 0.31 0.47 ψJB Junction-to-board characterization parameter 4.02 3.86 3.84 RθJC(bot) Junction-to-case (bottom) thermal resistance 1.06 n/a n/a (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) The package thermal resistance is calculated on a 4 layer JEDEC board. (3) Package DAP connected to PCB GND plane with 16 thermal vias (0.3 mm diameter). (4) ψJB (junction to board) is used when the main heat flow is from the junction to the GND pad. Please refer to Thermal Considerations section for more information on ensuring good system reliability and quality. 6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK03318 |
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