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SI3462-EVB Datasheet(PDF) 5 Page - Silicon Laboratories |
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SI3462-EVB Datasheet(HTML) 5 Page - Silicon Laboratories |
5 / 32 page Si3462-EVB Rev. 1.2 5 5.1. PSE Detection, Classification, Power-Up, and Power Removal The basic sequence for applying power is shown in Figure 5. The following is a description of the functions that must be performed in each phase. Figure 5. Detection, Classification, Power-Up, and Disconnect Sequence 5.1.1. Detection During the detection phase, the PSE probes with limited current and voltage to determine if a 25 k signature is present. A valid PD must present between 23.75 and 26.25 k in the range of 2.8 to 10 V with an offset (due to the bridge diodes) of up to 1.9 V and a parallel capacitance of between 0.05 and 0.12 µF. The Si3462-EVB uses a robust 3-point detection sequence to avoid inadvertently powering and damaging a non-PoE-enabled device. For endpoint applications, detection must be completed within 500 ms of applying a valid signature. When configured as a midspan, there is a possibility that the PSE circuit will compete with an endpoint PSE, and, as required by the IEEE specifications, the Si3462 waits at least two seconds after an unsuccessful detection cycle to repeat the detection process. tDET_CYCLE Time (msec) 2.8 V 10 V 15.5 V 44 V 57 V 20.5 V tCLASS_CYCLE tPWRUP |
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