Si5334

Rev. 1.2

5

Table 3. Performance Characteristics

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

PLL Acquisition Time

——

25

ms

PLL Tracking Range

5000

20,000

—

ppm

PLL Loop Bandwidth

—1.6

—

MHz

MultiSynth Frequency

Synthesis Resolution

Output frequency < Fvco/8

0

0

1

ppb

CLKIN Loss of Signal Assert

Time

—2.6

5

µs

CLKIN Loss of Signal Deassert

Time

0.01

0.2

1

µs

PLL Loss of Lock Detect Time

—5

10

ms

POR to Output Clock Valid

——

2

ms

Input-to-Output Propagation

Delay

Buffer Mode

(PLL Bypass)

—2.5

4

ns

Output-Output Skew

Rn divider = 11

——

100

ps

Programmable Initial

Phase Offset

–45

—

+45

ns

Phase Increment/Decrement

Accuracy

——

20

ps

Phase Increment/Decrement

Range

–45

—

+45

ns

Frequency range for phase

increment/decrement

—

—

3502

MHz

Phase Increment/Decrement

Update Rate

Pin control

—

—

1500

kHz

Frequency Increment/

Decrement Step Size

R divider not used3

1

—

See

Note 3

ppm

Frequency Increment/

Decrement Range

R divider not used3

—

—

3502

MHz

Frequency Increment/

Decrement Update Rate

Pin control2,3

—

—

1500

kHz

Notes:

1. Outputs at integer-related frequencies and using the same driver format.

2. Keep MultiSynth output frequency between 5 MHz to Fvco/8.

3. Only MultiSynth0 can have frequency inc/dec but MultiSynth0 can be routed to any output.

4. Spread spectrum is only available on clock outputs that are at 100 MHz and have the Rn divider set to 1.