Electronic Components Datasheet Search |
|
SI5335 Datasheet(PDF) 11 Page - Silicon Laboratories |
|
SI5335 Datasheet(HTML) 11 Page - Silicon Laboratories |
11 / 47 page Si5335 Rev. 1.4 11 Cycle-Cycle Jitter JCC N = 10,000 cycles Output MultiSynth operated in integer or fractional mode7 — 9 29 ps pk8 Random Jitter (12kHz–20MHz) RJ Output and feedback MultiSynth in integer or fractional mode7 — 0.7 1.5 ps RMS Deterministic Jitter DJ Output MultiSynth operated in fractional mode7 —3 15 ps pk-pk Output MultiSynth operated in integer mode7 —2 10 ps pk-pk Total Jitter (12kHz–20MHz) TJ =DJ+14xRJ (See Note 9) Output MultiSynth operated in fractional mode7 — 13 36 ps pk-pk Output MultiSynth operated in integer mode7 — 12 20 ps pk-pk Table 8. Jitter Specifications, Clock Generator Mode (Loop Bandwidth = 1.6 MHz)1,2,3 (Continued) (VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. All jitter measurements apply for LVDS/HCSL/LVPECL/CML output format with a low noise differential input clock and are made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation. 2. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration implements any single-ended output and any output is required to have jitter less than 2 ps rms, contact Silicon Labs for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS outputs have little to no effect upon jitter. 3. For best jitter performance, keep the single-ended clock input slew rates at pins 1 and 2 greater that 1.0 V/ns and the differential clock input slew rates greater than 0.3 V/ns. 4. DJ for PCI and GbE is < 5 ps pp 5. Output MultiSynth in Integer mode. 6. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter. See AN562 for details. Jitter is mesured with the Intel Clock Jitter Tool, Ver.1.6.4. 7. For any output frequency > 10 MHz. 8. Measured in accordance with JEDEC standard 65. 9. Rj is multiplied by 14; estimate the pp jitter from Rj over 212 rising edges. 10. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5. 11. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter. |
Similar Part No. - SI5335 |
|
Similar Description - SI5335 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |