Si5335

Rev. 1.4

11

Cycle-Cycle Jitter

N = 10,000 cycles

Output MultiSynth

operated in integer or

fractional mode7

—

9

29

ps pk8

Random Jitter

(12kHz–20MHz)

Output and feedback

MultiSynth in integer or

fractional mode7

—

0.7

1.5

ps RMS

Deterministic Jitter

Output MultiSynth

operated in fractional

mode7

—3

15

ps pk-pk

Output MultiSynth

operated in integer

mode7

—2

10

ps pk-pk

Total Jitter

(12kHz–20MHz)

(See Note 9)

Output MultiSynth

operated in fractional

mode7

—

13

36

ps pk-pk

Output MultiSynth

operated in integer

mode7

—

12

20

ps pk-pk

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Notes:

1. All jitter measurements apply for LVDS/HCSL/LVPECL/CML output format with a low noise differential input clock and

are made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.

2. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there

is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration

implements any single-ended output and any output is required to have jitter less than 2 ps rms, contact Silicon Labs

for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS

outputs have little to no effect upon jitter.

3. For best jitter performance, keep the single-ended clock input slew rates at pins 1 and 2 greater that 1.0 V/ns and the

differential clock input slew rates greater than 0.3 V/ns.

5. Output MultiSynth in Integer mode.

6. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.

See AN562 for details. Jitter is mesured with the Intel Clock Jitter Tool, Ver.1.6.4.

7. For any output frequency > 10 MHz.

8. Measured in accordance with JEDEC standard 65.

10. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.