SI5347 datasheet(4/59 Pages) SILABS

Part #	SI5347

Description	DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS

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Manufacturer	SILABS [Silicon Laboratories]

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Si5347/46

4

Rev. 1.1

2. Electrical Specifications

Table 1. Recommended Operating Conditions

(VDD =1.8 V ±5%, VDDA =3.3 V ±5%,TA = –40 to 85 °C)

Parameter

Symbol

Min

Typ

Max

Unit

Ambient Temperature

TA

–40

25

85

°C

Junction Temperature

TJMAX

——

125

°C

Core Supply Voltage

VDD

1.71

1.80

1.89

V

VDDA

3.14

3.30

3.47

V

Output Driver Supply Voltage

VDDO

3.14

3.30

3.47

V

2.38

2.50

2.62

V

1.71

1.80

1.89

V

Status Pin Supply Voltage

VDDS

3.14

3.30

3.47

V

1.71

1.80

1.89

V

Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.

Table 2. DC Characteristics

(VDD =1.8 V ±5%, VDDA =3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Core Supply Current

IDD

Si5347

Notes 1, 2

—

175

240

mA

Si5346

—

170

230

mA

IDDA

Si5347

—

120

130

mA

Si5346

120

130

mA

Notes:

1. Si5347 test configuration: 7 x 2.5 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors.

2. Si5346 test configuration: 4 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.

3. Differential outputs terminated into an AC coupled 100

 load.

4. LVCMOS outputs measured into a 5-inch 50

 PCB trace with 5 pF load. The LVCMOS outputs were set to

OUTx_CMOS_DRV = 3, which is the strongest driver setting. Refer to the Si5347/46 Family Reference Manual for

more details on register settings.

5. Detailed power consumption for any configuration can be estimated using ClockBuilder Pro when an evaluation board

(EVB) is not available. All EVBs support detailed current measurements for any configuration.

50

100

OUT

IDDO

Differential Output Test Configuration

0.1 µF

50

OUT

IDDO

Trace length 5

inches

50

4.7 pF

499



56



4.7 pF

499



56



50

 Scope Input

50

 Scope Input

0.1 µF

LVCMOS Output Test Configuration

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