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SI7020-A20-YM0R Datasheet(PDF) 6 Page - Silicon Laboratories |
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SI7020-A20-YM0R Datasheet(HTML) 6 Page - Silicon Laboratories |
6 / 36 page Si7020-A20 6 Rev. 1.1 Figure 1. I2C Interface Timing Diagram Table 3. I2C Interface Specifications1 1.9 VDD 3.6 V; TA = –40 to +85 °C (G grade) or –40 to +125 °C (I/Y grade) unless otherwise noted. Parameter Symbol Test Condition Min Typ Max Unit Hysteresis VHYS High-to-low versus low-to- high transition 0.05 x VDD —— V SCLK Frequency2 fSCL — — 400 kHz SCL High Time tSKH 0.6 — — µs SCL Low Time tSKL 1.3 — — µs Start Hold Time tSTH 0.6 — — µs Start Setup Time tSTS 0.6 — — µs Stop Setup Time tSPS 0.6 — — µs Bus Free Time tBUF Between Stop and Start 1.3 — — µs SDA Setup Time tDS 100 — — ns SDA Hold Time tDH 100 — — ns SDA Valid Time tVD;DAT From SCL low to data valid — — 0.9 µs SDA Acknowledge Valid Time tVD;ACK From SCL low to data valid — — 0.9 µs Suppressed Pulse Width3 tSPS 50 — — ns Notes: 1. All values are referenced to VIL and/or VIH. 2. Depending on the conversion command, the Si7020 may hold the master during the conversion (clock stretch). At above 100 kHz SCL, the Si7020 may also hold the master briefly for user register and device ID transactions. At the highest I2C speed of 400 kHz the stretching will be <50 µs. 3. Pulses up to and including 50 ns will be suppressed. SCL D6 1/fSCL tSKH SDA tSKL tSTH D5 D4 D0 R/W ACK tDS tDH Start Bit Stop Bit tBUF tSTS tVD : ACK tSPS tSP |
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