Functional Description

The ACT823 consists of nine D-type edge-triggered

flip-flops. These have TRI-STATE outputs for bus systems

organized with inputs and outputs on opposite sides. The

buffered clock (CP) and buffered Output Enable (OE) are

common to all flip-flops. The flip-flops will store the state of

their individual D inputs that meet the setup and hold time re-

quirements on the LOW-to-HIGH CP transition. With OE

LOW, the contents of the flip-flops are available at the out-

puts. When OE is HIGH, the outputs go to the high imped-

ance state. Operation of the OE input does not affect the

state of the flip-flops. In addition to the Clock and Output En-

able pins, there are Clear (CLR) and Clock Enable (EN) pins.

These devices are ideal for parity bus interfacing in high per-

formance systems.

When CLR is LOW and OE is LOW, the outputs are LOW.

When CLR is HIGH, data can be entered into the flip-flops.

When EN is LOW, data on the inputs is transferred to the

outputs on the LOW-to-HIGH clock transition. When the EN

is HIGH, the outputs do not change state, regardless of the

data or clock input transitions.

Function Table

Inputs

Internal

Output

Function

OE

CLR

EN

CP

D

Q

O

H

X

L

N

L

L

Z

High Z

H

X

L

N

H

H

Z

High Z

H

L

X

X

X

L

Z

Clear

L

L

X

X

X

L

L

Clear

H

H

H

X

X

NC

Z

Hold

L

H

H

X

X

NC

NC

Hold

H

H

L

N

L

L

Z

Load

H

H

L

N

H

H

Z

Load

L

H

L

N

L

L

L

Load

L

H

L

N

H

H

H

Load

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

N = LOW-to-HIGH Transition

NC = No Change

Logic Diagram

DS100253-5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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