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ADP5054ACPZ-R7 Datasheet(PDF) 1 Page - Analog Devices

Part # ADP5054ACPZ-R7
Description  Quad Buck Regulator Integrated Power Solution
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADP5054ACPZ-R7 Datasheet(HTML) 1 Page - Analog Devices

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Quad Buck Regulator
Integrated Power Solution
Data Sheet
ADP5054
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
FEATURES
Wide input voltage range: 4.5 V to 15.5 V
±1.5% output accuracy over full temperature range
250 kHz to 2 MHz adjustable switching frequency with
individual ½× frequency option
Power regulation
Channel 1 and Channel 2
Programmable 2 A/4 A/6 A sync buck regulators with
low-side FET drivers
Channel 3 and Channel 4: 2.5 A sync buck regulators
Flexible parallel operation
Single 12 A output (Channel 1 and Channel 2 in parallel)
Single 5 A output (Channel 3 and Channel 4 in parallel)
Low 1/f noise density
40 µV rms at 0.8 VREF for 10 Hz to 100 kHz
Precision enable with 0.811 V accurate threshold
Active output discharge switch
FPWM/PSM mode selection
Frequency synchronization input or output
Power-good flag for Channel 1 output
UVLO, OCP, and TSD protection
48-lead, 7 mm × 7 mm LFCSP
−40°C to +125°C operational junctional temperature range
APPLICATIONS
FPGA and processor applications
Small cell base stations
Security and surveillance
Medical applications
TYPICAL APPLICATION CIRCUIT
OSCILLATOR
INTERNAL
VREG
100mA
Q1
Q2
L1
L2
VREG
SYNC/MODE
ADP5054
RT
FB1
BST1
SW1
DL1
PGND
DL2
SW2
BST2
FB2
L3
BST3
SW3
FB3
PGND3
L4
BST4
SW4
FB4
PGND4
VREG
PVIN1
PVIN2
COMP2
EN2
PVIN3
COMP3
EN3
PVIN4
COMP4
EN4
C2
C1
C4
C3
C5
C6
C7
C9
C10
C11
C12
C13
4.5V TO 15.5V
VOUT1
VOUT2
VOUT3
VOUT4
PWRGD
VREG
EXPOSED PAD
C0
VDD
CFG34
CFG12
(SS, 1/2 ×
f
SW,
PARALLEL)
(SS, 1/2 ×
f
SW,
PARALLEL,
SCLKSET)
C8
COMP1
EN1
VREG
VREG
CHANNEL 1
BUCK
(2A/4A/6A)
CHANNEL 2
BUCK
(2A/4A/6A)
CHANNEL 3
BUCK
(2A)
CHANNEL 4
BUCK
(2A)
Figure 1.
GENERAL DESCRIPTION
The ADP5054 combines four high performance buck regulators in
a 48-lead LFCSP package that meets demanding performance and
board space requirements. The device enables direct connection
to high input voltages of up to 15.5 V with no preregulators.
Channel 1 and Channel 2 integrate high-side power MOSFETs and
low-side MOSFET drivers. External NFETs can be used in low-side
power devices to achieve an efficiency optimized solution and
to deliver a programmable output current of 2 A, 4 A, or 6 A.
Combining Channel 1 and Channel 2 in a parallel configuration
provides a single output with up to 12 A of current.
Channel 3 and Channel 4 integrate both high-side and low-side
MOSFETs to deliver an output current of 2.5 A. Combining
Channel 3 and Channel 4 in a parallel configuration can
provide a single output with up to 5 A of current.
The switching frequency of the ADP5054 can be programmed
or synchronized to an external clock from 250 kHz to 2 MHz,
and an individual ½× frequency configuration is available for
each channel.
The ADP5054 contains an individual precision enable pin on each
channel for easy power-up sequencing. The internal low 1/f noise
reference is implemented in the ADP5054 for noise sensitive
applications.
Table 1. Related Products
Model
Channels
I2C
Package
ADP5050
Four bucks, one LDO
Yes
48-Lead LFCSP
ADP5051
Four bucks, supervisory
Yes
48-Lead LFCSP
ADP5052
Four bucks, one LDO
No
48-Lead LFCSP
ADP5053
Four bucks, supervisory
No
48-Lead LFCSP
ADP5054
Four high current bucks
No
48-Lead LFCSP


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