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SI53302 Datasheet(PDF) 9 Page - Silicon Laboratories |
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SI53302 Datasheet(HTML) 9 Page - Silicon Laboratories |
9 / 34 page Si53302 Rev. 1.1 9 Table 11. Additive Jitter, Differential Clock Input VDD Input1,2 Output Additive Jitter (fs rms, 12 kHz to 20 MHz)3 Freq (MHz) Clock Format Amplitude VIN (Single-Ended, Peak-to-Peak) Differential 20%-80% Slew Rate (V/ns) Clock Format Typ Max 3.3 725 Differential 0.15 0.637 LVPECL 45 65 3.3 725 Differential 0.15 0.637 LVDS 50 65 3.3 156.25 Differential 0.5 0.458 LVPECL 160 185 3.3 156.25 Differential 0.5 0.458 LVDS 150 200 2.5 725 Differential 0.15 0.637 LVPECL 45 65 2.5 725 Differential 0.15 0.637 LVDS 50 65 2.5 156.25 Differential 0.5 0.458 LVPECL 145 185 2.5 156.25 Differential 0.5 0.458 LVDS 145 195 Notes: 1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. 2. AC-coupled differential inputs. 3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1. |
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