Si53305

8

Rev. 1.0

Output Disable Time

F=1MHz

—

2000

—

ns

F = 100 MHz

—

30

—

ns

F = 725 MHz

—

5

—

ns

Output to Output Skew2

LVCMOS (12 mA drive to no load)

—

50

120

ps

LVPECL

—

35

70

ps

LVDS

—

35

70

ps

Part to Part Skew3

Differential

—

—

150

ps

Power Supply Noise

Rejection4

PSRR

10 kHz sinusoidal noise

—

–63

—

dBc

100 kHz sinusoidal noise

—

–62

—

dBc

500 kHz sinusoidal noise

—

–58

—

dBc

1 MHz sinusoidal noise

—

–55

—

dBc

Table 10. AC Characteristics (Continued)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Notes:

1.

HCSL measurements were made with receiver termination. See Figure 9 on page 19.

2.

Output to Output skew specified for outputs with an identical configuration.

3.

Defined as skew between any output on different devices operating at the same supply voltage, temperature, and

equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross

points.

4.

amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details.