SI53312 datasheet(1/33 Pages) SILABS

Part #	SI53312

Description	1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

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Manufacturer	SILABS [Silicon Laboratories]

Direct Link	http://www.silabs.com

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1 / 33 page

Rev. 1.0 9/15

Si53312

1:10 L OW J ITTER U NIVERSAL B UFFER/L EVEL

TRANSLATOR WITH 2:1 I NPUT M UX (<1.25 GH Z)

Features

Applications

Description

The Si53312 is an ultra low jitter ten output differential buffer with pin-selectable

output clock signal format and divider selection. The Si53312 features a 2:1 mux,

making it ideal for redundant clocking applications. The Si53312 utilizes Silicon

Laboratories' advanced CMOS technology to fanout clocks from dc to 1.25 GHz

with guaranteed low additive jitter, low skew, and low propagation delay variability.

The Si53312 features minimal cross-talk and provides superior supply noise

rejection, simplifying low jitter clock distribution in noisy environments.

Independent core and output bank supply pins provide integrated level translation

without the need for external circuitry.

Functional Block Diagram



10 differential or 20 LVCMOS outputs



Ultra-low additive jitter: 45 fs rms



Wide frequency range:

dc to 1.25 GHz



Any-format input with pin selectable

output formats: LVPECL, Low Power

LVPECL, LVDS, CML, HCSL,

LVCMOS



2:1 mux with hot-swappable inputs



Asynchronous output enable



Output clock division: /1, /2, /4

(/2 and /4 for dc to 725 MHz)



Low output-output skew: <70 ps



Low propagation delay variation:

<400 ps



Independent VDD and VDDO :

1.8/2.5/3.3 V



Excellent power supply noise

rejection (PSRR)



Selectable LVCMOS drive strength to

tailor jitter and EMI performance



Small size: 44-QFN (7 mm x 7 mm)



RoHS compliant, Pb-free



Industrial temperature range:

–40 to +85 °C



High-speed clock distribution



Ethernet switch/router



Optical Transport Network (OTN)



SONET/SDH



PCI Express Gen 1/2/3



Storage



Telecom



Industrial



Servers



Backplane clock distribution

VREF

DivA

DivB

Power

Supply

Filtering

Vref

Generator

VDDOB

OEB

SFOUTB[1:0]

Q0, Q1, Q2, Q3, Q4

OEA

VDDOA

SFOUTA[1:0]

DIVA

DIVB

/CLK0

CLK0

/CLK1

CLK1

Q5, Q6, Q7, Q8, Q9

CLK_SEL

Switching

Logic

Patents pending

Ordering Information:

See page 28.

Pin Assignments

Si53312

GND

PAD

27

26

25

24

23

29

28

30

32

31

33

7

8

9

10

11

5

6

4

2

3

1

CLK_SEL

Q0

Q1

Q2

Q7

Q8

Q9

GND

DIVA

SFOUTA[1]

SFOUTA[0]

DIVB

SFOUTB[1]

SFOUTB[0]

NC

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Manufacturer	Part #	Datasheet	Description
Silicon Laboratories	SI53302	1Mb / 34P	1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX
	SI53311	1Mb / 30P	1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX
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Skyworks Solutions Inc.	SI53312	2Mb / 33P	1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX (<1.25 GHZ) Rev. 1.0
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Skyworks Solutions Inc.	SI53311	1Mb / 30P	1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX (<1.25 GHZ) Rev. 0.4
Silicon Laboratories	SI53304	1Mb / 33P	1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE
Skyworks Solutions Inc.	SI53315	1Mb / 30P	1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE (<1.25 GHZ) Rev. 0.4
Skyworks Solutions Inc.	SI53314	2Mb / 32P	1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE (<1.25 GHZ) Rev. 1.0
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