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SI53312 Datasheet(PDF) 1 Page - Silicon Laboratories |
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SI53312 Datasheet(HTML) 1 Page - Silicon Laboratories |
1 / 33 page Rev. 1.0 9/15 Copyright © 2015 by Silicon Laboratories Si53312 Si53312 1:10 L OW J ITTER U NIVERSAL B UFFER/L EVEL TRANSLATOR WITH 2:1 I NPUT M UX (<1.25 GH Z) Features Applications Description The Si53312 is an ultra low jitter ten output differential buffer with pin-selectable output clock signal format and divider selection. The Si53312 features a 2:1 mux, making it ideal for redundant clocking applications. The Si53312 utilizes Silicon Laboratories' advanced CMOS technology to fanout clocks from dc to 1.25 GHz with guaranteed low additive jitter, low skew, and low propagation delay variability. The Si53312 features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Independent core and output bank supply pins provide integrated level translation without the need for external circuitry. Functional Block Diagram 10 differential or 20 LVCMOS outputs Ultra-low additive jitter: 45 fs rms Wide frequency range: dc to 1.25 GHz Any-format input with pin selectable output formats: LVPECL, Low Power LVPECL, LVDS, CML, HCSL, LVCMOS 2:1 mux with hot-swappable inputs Asynchronous output enable Output clock division: /1, /2, /4 (/2 and /4 for dc to 725 MHz) Low output-output skew: <70 ps Low propagation delay variation: <400 ps Independent VDD and VDDO : 1.8/2.5/3.3 V Excellent power supply noise rejection (PSRR) Selectable LVCMOS drive strength to tailor jitter and EMI performance Small size: 44-QFN (7 mm x 7 mm) RoHS compliant, Pb-free Industrial temperature range: –40 to +85 °C High-speed clock distribution Ethernet switch/router Optical Transport Network (OTN) SONET/SDH PCI Express Gen 1/2/3 Storage Telecom Industrial Servers Backplane clock distribution VREF DivA DivB Power Supply Filtering Vref Generator VDDOB OEB SFOUTB[1:0] Q0, Q1, Q2, Q3, Q4 Q0, Q1, Q2, Q3, Q4 OEA VDDOA SFOUTA[1:0] DIVA DIVB /CLK0 CLK0 /CLK1 CLK1 Q5, Q6, Q7, Q8, Q9 Q5, Q6, Q7, Q8, Q9 CLK_SEL Switching Logic Patents pending Ordering Information: See page 28. Pin Assignments Si53312 GND PAD 27 26 25 24 23 29 28 30 32 31 33 7 8 9 10 11 5 6 4 2 3 1 CLK_SEL Q0 Q0 Q1 Q1 Q2 Q2 Q7 Q7 Q8 Q8 Q9 Q9 GND DIVA SFOUTA[1] SFOUTA[0] DIVB SFOUTB[1] SFOUTB[0] NC NC |
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