CDCEL824PWR datasheet(7/33 Pages) TI1

Part #	CDCEL824PWR

Description	Programmable 2-PLL Clock Synthesizer

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Manufacturer	TI1 [Texas Instruments]

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f - Frequency (MHz)

10

50

90

130

170

200

0

10

20

30

40

50

60

D001

All PLL Off

1 PLL On

2 PLL On

fOUT - Output Frequency (MHz)

10

50

90

130

170

200

0

1

2

3

4

5

6

D002

All Outputs Off

1 Output On

3 Outputs On

CDCEL824

www.ti.com

SCAS945A – JUNE 2015 – REVISED SEPTEMBER 2015

7.6 CLK_IN Timing Requirements

over recommended ranges of supply voltage, load, and operating free-air temperature

MIN

NOM

MAX

UNIT

PLL bypass mode

0

130

fCLK

LVCMOS clock input frequency

MHz

PLL mode

8

130

tr / tf

Rise and fall time CLK signal (20% to 80%)

3

ns

dutyCLK

Duty cycle CLK at VDD / 2

40%

60%

7.7 SDA/SCL Timing Requirements

STANDARD MODE

FAST MODE

(SeeFigure 5)

UNIT

MIN

MAX

MIN

MAX

fSCL

SCL clock frequency

0

100

0

400

kHz

tsu(START)

START setup time (SCL high before SDA low)

4.7

0.6

μs

th(START)

START hold time (SCL low after SDA low)

4

0.6

μs

tw(SCLL)

SCL low-pulse duration

4.7

1.3

μs

tw(SCLH)

SCL high-pulse duration

4

0.6

μs

th(SDA)

SDA hold time (SDA valid after SCL low)

0

3.45

0

0.9

μs

tsu(SDA)

SDA setup time

250

100

ns

tr

SCL/SDA input rise time

1000

300

ns

tf

SCL/SDA input fall time

300

ns

tsu(STOP)

STOP setup time

4

0.6

μs

tBUS

Bus free time between a STOP and START condition

4.7

1.3

μs

7.8 EEPROM Specification

MIN

TYP

MAX

UNIT

EEcyc

Programming cycles of EEPROM

100

1000

cycles

EEret

Data retention

10

years

7.9 Typical Characteristics

Figure 1. Supply Current vs PLL Frequency

Figure 2. Output Current vs Output Frequency

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