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CDCM7005RGZRG4 Datasheet(PDF) 2 Page - Texas Instruments

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Part # CDCM7005RGZRG4
Description  3.3-V High Performance Clock Synchronizer and Jitter Cleaner
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM7005RGZRG4 Datasheet(HTML) 2 Page - Texas Instruments

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CDCM7005
SCAS793F – JUNE 2005 – REVISED JULY 2015
www.ti.com
Table of Contents
9.2
Functional Block Diagram ....................................... 16
1
Features .................................................................. 1
9.3
Feature Description................................................. 16
2
Applications ........................................................... 1
9.4
Device Functional Modes........................................ 24
3
Description ............................................................. 1
9.5
Programming........................................................... 25
4
Revision History..................................................... 2
10
Application and Implementation........................ 34
5
Description (continued)......................................... 4
10.1
Application Information.......................................... 34
6
Pin Configuration and Functions ......................... 4
10.2
Typical Application ............................................... 37
7
Specifications......................................................... 7
11
Power Supply Recommendations ..................... 40
7.1
Absolute Maximum Ratings ...................................... 7
12
Layout................................................................... 40
7.2
ESD Ratings.............................................................. 7
12.1
Layout Guidelines ................................................. 40
7.3
Recommended Operating Conditions ....................... 7
12.2
Layout Example .................................................... 41
7.4
Thermal Information .................................................. 8
13
Device and Documentation Support ................. 43
7.5
Electrical Characteristics........................................... 8
13.1
Community Resources.......................................... 43
7.6
Timing Requirements .............................................. 10
13.2
Trademarks ........................................................... 43
7.7
Typical Characteristics ............................................ 11
13.3
Electrostatic Discharge Caution ............................ 43
8
Parameter Measurement Information ................ 12
13.4
Glossary ................................................................ 43
9
Detailed Description ............................................ 15
14
Mechanical, Packaging, and Orderable
9.1
Overview ................................................................. 15
Information ........................................................... 43
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (February 2013) to Revision F
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision D (August 2009) to Revision E
Page
Changed PLL_LOCK pin description, replaced cycle-slip text. .............................................................................................. 5
Changed the Frequency Hold-Over Mode section ............................................................................................................... 22
Changed text From: Cycle-Slip To: Frequency Offset in Figure 21 ..................................................................................... 23
Changed Note 1 of table Word 3.......................................................................................................................................... 29
Changed table Word 3, Cycle Slip (Bit 6) To: Frequency Offset.......................................................................................... 29
Changed table Lock-Detect Window (Word 3) - Clip slip To: Frequency offset, and Note 2 ............................................... 32
Changes from Revision C (December 2007) to Revision D
Page
Added text to the CTRL_CLK pin - Unused or floating inputs must be tied to proper logic level. A 20k
Ω or larger
pull
−up resistor to VCC is recommended. ............................................................................................................................. 4
Added text to the CTRL_DATA pin - Unused or floating inputs must be tied to proper logic level. A 20k
Ω or larger
pull
−up resistor to VCC is recommended. ............................................................................................................................. 4
Added text to the CTRL_LE pin - Unused or floating inputs must be tied to proper logic level. A 20k
Ω or larger
pull
−up resistor to VCC is recommended. ............................................................................................................................. 4
Added text to the PD pin - It is recommended to ramp up the PD with the same time as VCC and AVCC or later. The
ramp up rate of the PD should not be faster than the ramp up rate of VCC and AVCC. .......................................................... 5
Changed VCC pin text From: 3.3-V supply. There is no internal connection between VCC and AVCC. It is
recommended that AVCC use its own supply filter. To: 3.3-V supply. VCC and AVCC should always have the same
supply voltage. It is recommended that AVCC use its own supply filter. ................................................................................. 6
Added text to the SPI CONTROL INTERFACE section - Unused or floating inputs must be tied to proper logic level.
2
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