CDCM7005RGZTG4 datasheet(1/52 Pages) TI1

Part #	CDCM7005RGZTG4

Description	3.3-V High Performance Clock Synchronizer and Jitter Cleaner

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CDCM7005

VCXO

LF

VCXO

IN

VCXO

IN

CP

OUT

PRI

REF

YnA

YnB

OSC

DAC

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Design

CDCM7005

SCAS793F – JUNE 2005 – REVISED JULY 2015

CDCM7005 3.3-V High Performance Clock Synchronizer and Jitter Cleaner

1 Features

3 Description

The CDCM7005 is a high-performance, low phase

1

•

High Performance LVPECL and LVCMOS PLL

noise

and

low

skew

clock

synchronizer

that

Clock Synchronizer

synchronizes a VCXO (voltage controlled crystal

•

Two Reference Clock Inputs (Primary and

oscillator) or VCO (voltage controlled oscillator)

Secondary Clock) for Redundancy Support With

frequency to one of the two reference clocks. The

Manual or Automatic Selection

programmable pre-divider M and the feedback-

dividers N and P give a high flexibility to the

•

Accepts LVCMOS Input Frequencies up to 200

frequency ratio of the reference clock to VC(X)O

MHz

•

VCXO_IN Clock is Synchronized to One of the

VC(X)O_IN clock operates up to 2.2 GHz. Through

the selection of external VC(X)O and loop filter

Two Reference Clocks

components, the PLL loop bandwidth and damping

•

VCXO_IN Frequencies Up to 2.2 GHz (LVPECL)

factor can be adjust to meet different system

•

Outputs Can Be a Combination of LVPECL and

requirements.

LVCMOS (Up to Five Differential LVPECL Outputs

The CDCM7005 can lock to one of two reference

or up to 10 LVCMOS Outputs)

clock inputs (PRI_REF and SEC_REF), supports

•

Output Frequency is Selectable by ×1, /2, /3, /4,

frequency hold-over mode and fast-frequency-locking

/6, /8, /16 on Each Output Individually

for fail-safe and increased system redundancy. The

•

Efficient Jitter Cleaning From Low PLL Loop

outputs of the CDCM7005 are user definable and can

be any combination of up to five LVPECL outputs or

Bandwidth

up

to

10

LVCMOS

outputs.

The

built

in

•

Low Phase Noise PLL Core

synchronization latches ensure that all outputs are

•

Programmable Phase Offset (PRI_REF and

synchronized for low output skew.

SEC_REF to Outputs)

Device Information(1)

•

Wide Charge Pump Current Range From

200

μA to 3 mA

PART NUMBER

PACKAGE

BODY SIZE (NOM)

VQFN (48)

7.00 mm × 7.00 mm

•

Dedicated Charge Pump Supply (VCC_CP) for

CDCM7005

Wide Tuning Voltage Range VCOs

BGA (64)

8.00 mm × 8.00 mm

•

Presets Charge Pump to VCC_CP/2 for Fast

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Center-Frequency Setting of VC(X)O

•

Analog and Digital PLL Lock Indication

Typical Application Schematic

•

Provides VBB Bias Voltage Output for Single-

Ended Input Signals (VCXO_IN)

•

Frequency Hold-Over Mode Improves Fail-Safe

Operation

•

Power-up Control Forces LVPECL Outputs to 3-

State at VCC < 1.5 V

•

SPI Controllable Device Setting

•

3.3-V Power Supply

•

Packaged in 64-Pin BGA (0.8 mm Pitch – ZVA) or

48-Pin QFN (RGZ)

•

Industrial Temperature Range –40°C to 85°C

2 Applications

•

Wireless Infrastructure

•

SONET

•

Data Communication

•

Test Equipment

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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CDCM7005RGZTG4 Datasheet(PDF) 1 Page - Texas Instruments

CDCM7005RGZTG4 Datasheet(HTML) 1 Page - Texas Instruments

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