LMK00334RTVR datasheet(6/31 Pages) TI1

Part #	LMK00334RTVR

Description	Four-Output PCIe/Gen1/Gen2/Gen3 Clock Buffer/Level Translator

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Manufacturer	TI1 [Texas Instruments]

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LMK00334

SNAS635A – DECEMBER 2013 – REVISED OCTOBER 2014

www.ti.com

6.5 Electrical Characteristics

Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C

≤ TA ≤ 85 °C, CLKin driven

differentially, input slew rate

≥ 3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, TA

= 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured.

(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CURRENT CONSUMPTION (2)

CLKinX selected

8.5

10.5

mA

Core Supply Current, All Outputs

ICC_CORE

Disabled

OSCin selected

10

13.5

mA

ICC_HCSL

50

58.5

mA

ICC_CMOS

3.5

5.5

mA

Includes Output Bank Bias and Load

Additive Output Supply Current,

ICCO_HCSL

Currents for both banks, RT = 50

Ω on all

65

81.5

mA

HCSL Banks Enabled

outputs

Vcco = 3.3 V ±5%

9

10

mA

Additive Output Supply Current,

ICCO_CMOS

200 MHz, CL = 5 pF

LVCMOS Output Enabled

Vcco = 2.5V ± 5%

7

8

mA

POWER SUPPLY RIPPLE REJECTION (PSRR)

156.25 MHz

-72

Ripple-Induced Phase Spur Level(3)

PSRRHCSL

dBc

Differential HCSL Output

312.5 MHz

-63

CMOS CONTROL INPUTS (CLKin_SELn, CLKout_TYPEn, REFout_EN)

VIH

High-Level Input Voltage

1.6

Vcc

V

VIL

Low-Level Input Voltage

GND

0.4

V

IIH

High-Level Input Current

VIH = Vcc, Internal pull-down resistor

50

μA

IIL

Low-Level Input Current

VIL = 0 V, Internal pull-down resistor

-5

0.1

μA

CLOCK INPUTS (CLKin0/CLKin0*, CLKin1/CLKin1*)

Functional up to 400 MHz

Output frequency range and timing specified

fCLKin

Input Frequency Range(4)

DC

400

MHz

per output type (refer to LVCMOS output

specifications)

VIHD

Differential Input High Voltage

Vcc

V

VILD

Differential Input Low Voltage

CLKin driven differentially

GND

V

VID

Differential Input Voltage Swing(5)

0.15

1.3

V

VID = 150 mV

0.25

Vcc - 1.2

Differential Input CMD Common

VCMD

VID = 350 mV

0.25

Vcc - 1.1

V

Mode Voltage

VID = 800 mV

0.25

Vcc - 0.9

VIH

Single-Ended Input IH High Voltage

VCC

V

VIL

Single-Ended Input IL Low Voltage

GND

V

CLKinX driven single-ended (AC or DC

coupled), CLKinX* AC coupled to GND or

VI_SE

Single-Ended Input Voltage Swing(4)

0.3

2

Vpp

externally biased within VCM range

Single-Ended Input CM Common

VCM

0.25

VCC - 1.2

V

Mode Voltage

fCLKin0 = 100 MHz

-84

fCLKin0 = 200 MHz

-82

fOFFSET > 50 kHz,

ISOMUX

Mux Isolation, CLKin0 to CLKin1

dBc

PCLKinX = 0 dBm

fCLKin0 = 500 MHz

-71

fCLKin0 = 1000 MHz

-65

(1)

The output supply voltages or pins (VCCOA, VCCOB, and VCCOC) will be called VCCO in general when no distinction is needed, or when the

output supply can be inferred from the output bank/type.

(2)

See Power Supply and Thermal Considerations for more information on current consumption and power dissipation calculations.

(3)

Power supply ripple rejection, or PSRR, is defined as the single-sideband phase spur level (in dBc) modulated onto the clock output

when a single-tone sinusoidal signal (ripple) is injected onto the Vcco supply. Assuming no amplitude modulation effects and small index

modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as

follows: DJ (ps pk-pk) = [ (2 * 10(PSRR / 20)) / (

π * fCLK) ] * 1E12

(4)

Specification is ensured by characterization and is not tested in production.

(5)

See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.

6

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