SI4702-EVB datasheet(8/44 Pages) SILABS

Part #	SI4702-EVB

Description	Si4700/01/02/03 EVALUATION BOARD USER?셎 GUIDE

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Manufacturer	SILABS [Silicon Laboratories]

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Si4700/01/02/03-EVB

8

Rev. 0.9

Table 1. EVB Configuration Matrix

#

Configuration

Variable

Value of Configuration

Variable

Hardware Changes

Constraints

1

Reference clock

source

Oscillator on baseboard.

None (Default option).

None

2

Reference clock

source

External clock through J6.

Depopulate R19 and popu-

late R21 with a 0

 resistor.

32.768 kHz, CMOS switch-

ing levels at VIO supply level.

3

Reference clock

source

On-chip internal oscillator

utilizing crystal on daugh-

ter card.

Depopulate R2 and R3 from

bottom of Si4700/01/02/03

daughter card.

GPIO3 is no longer available

and XOSCEN must be

selected when starting the

GUI.

4*

Power supply

source

USB; J1.

Position switch, SW1, to

USB POWER.

Cannot supply any voltages

via J4.

5*

Power supply

source

Power brick; J7.

Position switch, SW1, to

EXT POWER.

Cannot supply any voltages

via J4. Power brick must sup-

ply 5–26 V.

6*

Power supply

source

Bench supply; J4.

Depopulate R1, R2, and

R4.

See Section 3.1.3.

7

VIO source

Output of U2.

None (Default option).

5–26 V input using configura-

tion option 4, 5, or 6.

8

VIO source

Direct from VMCU/VIO

terminal of J4.

Depopulate U2 and popu-

late R30 with a 0

 resistor.

3.0–3.6 V input at VMCU/VIO

terminal of J4. Can only be

used in conjunction with con-

figuration option #6.

9

VA/VD source

Output of U3.

None (Default option).

5–26 V input using configura-

tion option 4, 5, or 6.

10

VA/VD source

Direct from VRADIO

terminal of J5.

Depopulate R14 and popu-

late R25 with a 0

 resistor.

2.7–5.5 V input at VMCU/VIO

terminal of J4. Can only be

used in conjunction with

configuration option #6.

*Note: For more information, see Section "3.1.3. Power Supply Network" on page 5.

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