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ADC31JB68RTAT Datasheet(PDF) 11 Page - Texas Instruments |
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ADC31JB68RTAT Datasheet(HTML) 11 Page - Texas Instruments |
11 / 74 page ADC31JB68 www.ti.com SLASE60A – SEPTEMBER 2015 – REVISED SEPTEMBER 2015 Electrical Characteristics - Interface (continued) Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC Sampling Rate = 500 MSPS, 50% clock duty cycle, VA3.0 = 3 V; VA1.8 = 1.8 V; VA1.2 = VACLK1.2 = 1.2 V; –1 dBFS differential input; R(term) = 100 Ω (unless otherwise noted). See the Interface Circuits section. PARAMETER NOTES MIN TYP MAX UNIT Z(rdiff) Input termination resistance(2) Differential resistance at DC 100 Ω CT Input capacitance(2) Differential 1 pF SERDES OUTPUT (SO0+/-, SO1+/-) Meets JESD204B LV-OIF-11G-SR Standard Differential peak-peak voltage De-emphasis disabled (DEM = 0) VOD = 0 400 VOD = 1 470 VOD = 2 540 VOD Output differential voltage(3) mV VOD = 3 610 VOD = 4 670 VOD = 5 740 VOD = 6 790 VOD = 7 840 Configurable via SPI VOD configured to 4 DEM=0 0.0 DEM=1 –0.8 DEM=2 –2.4 R(deepm) Transmitter de-emphasis range dB DEM=3 –3.8 DEM=4 –4.9 DEM=5 –6.3 DEM=6 –7.7 DEM=7 –10.3 Transmitter terminals shorted to each other ISC Transmitter short circuit current 23 mA or ground, power on Z(ddiff) Differential output impedance(4) 100 Ω Relative to 100 Ω Differential output return loss RL(ddiff) For frequencies from 100 MHz to 0.75 x –8.5 dB magnitude Baud Rate; Default VOD and DEM. SCLK, SDI, CSB INPUT Inputs are compatible with 1.2-V up to 3-V VIH Logical 1 input voltage 0.9 V logic. VIL Logical 0 input voltage 0.3 V IIN0 Logic low input current 4 nA IIN1 Logic high input current –8 nA CIN Input capacitance 2 pF SDO/OVR OUTPUT VOH Logical 1 output voltage(5) VSPI = 1.2, 1.8, or 3 V ; Configurable via SPI VSPI – 0.2 VSPI (5) V VOL Logical 0 output voltage(5) 0 0.3 V +ISC Logic high short circuit current VSPI = 1.8 V 9 mA –ISC Logic low short circuit current VSPI = 1.8 V –14 mA (3) Specification applies to the electrical level diagram of Figure 28 (4) Specification applies to the electrical circuit diagram of Figure 29 (5) The SPI_CFG register must be changed to a supported output logic level after power up and before a SPI read command is executed. Until that time, the output voltage on SDO/OVR may be as high as the VA3.0 supply during a SPI read command. The SDO/OVR output is high-Z at all times except during a read command. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: ADC31JB68 |
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