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ADS52J90ZZE Datasheet(PDF) 5 Page - Texas Instruments |
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ADS52J90ZZE Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 149 page  ADS52J90 www.ti.com SBAS690B – MAY 2015 – REVISED AUGUST 2015 Pin Functions(1) PIN I/O DESCRIPTION NAME NO. A4, E6, F6, G5, G6, M5, AVDD_1P8 P 1.8-V analog supply voltage M6, N6, P6, V4 B4, C4, D4, H5, H6, J5, AVSS J6, K5, K6, L5, L6, R4, R5, G Analog ground T4, T5, U4, U6, V6 CLKM U5 Differential clock input pins. A single-ended clock is also supported. I See the Clock Input section for further details. CLKP V5 CML1_OUTM A10 O JESD output lane 1 CML1_OUTP A9 CML2_OUTM B11 O JESD output lane 2 CML2_OUTP A11 CML3_OUTM D11 O JESD output lane 3 CML3_OUTP C11 CML4_OUTM F11 O JESD output lane 4 CML4_OUTP E11 CML5_OUTM V10 O JESD output lane 5 CML5_OUTP V9 CML6_OUTM U11 O JESD output lane 6 CML6_OUTP V11 CML7_OUTM R11 O JESD output lane 7 CML7_OUTP T11 CML8_OUTM N11 O JESD output lane 8 CML8_OUTP P11 DCLKM K11 O LVDS bit clock output DCLKP J11 DOUTM1 B10 O LVDS data lane 1 DOUTP1 B9 DOUTM2 C10 O LVDS data lane 2 DOUTP2 C9 DOUTM3 D10 O LVDS data lane 3 DOUTP3 D9 DOUTM4 E10 O LVDS data lane 4 DOUTP4 E9 DOUTM5 F10 O LVDS data lane 5 DOUTP5 F9 DOUTM6 G10 O LVDS data lane 6 DOUTP6 G9 DOUTM7 H10 O LVDS data lane 7 DOUTP7 H9 DOUTM8 G11 O LVDS data lane 8 DOUTP8 H11 DOUTM9 M11 O LVDS data lane 9 DOUTP9 L11 DOUTM10 L10 O LVDS data lane 10 DOUTP10 L9 DOUTM11 M10 O LVDS data lane 11 DOUTP11 M9 DOUTM12 N10 O LVDS data lane 12 DOUTP12 N9 (1) If the JESD interface is not used, then do not connect the CMLx, SYNCx, and SYSREFx pins. If the LVDS interface is not used, then do not connect DOUTx, DCLKx, and FCLKx. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ADS52J90 |
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