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ADS1298RIZXGR Datasheet(PDF) 2 Page - Texas Instruments

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Part # ADS1298RIZXGR
Description  Low-Power, 8-Channel, 24-Bit Analog Front-End for Biopotential Measurements
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADS1298RIZXGR Datasheet(HTML) 2 Page - Texas Instruments

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ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R
SBAS459K – JANUARY 2010 – REVISED AUGUST 2015
www.ti.com
Table of Contents
9.4
Device Functional Modes........................................ 51
1
Features .................................................................. 1
9.5
Programming........................................................... 59
2
Applications ........................................................... 1
9.6
Register Maps ......................................................... 65
3
Description ............................................................. 1
10
Application and Implementation........................ 84
4
Revision History..................................................... 2
10.1
Application Information.......................................... 84
5
Device Comparison ............................................... 5
10.2
Typical Applications .............................................. 89
6
Pin Configuration and Functions ......................... 6
11
Power Supply Recommendations ..................... 96
7
Specifications....................................................... 12
11.1
Power-Up Sequencing .......................................... 96
7.1
Absolute Maximum Ratings .................................... 12
11.2
Connecting to Unipolar (3 V or 1.8 V) Supplies.... 97
7.2
ESD Ratings............................................................ 12
11.3
Connecting to Bipolar (±1.5 V or ±1.8 V)
7.3
Recommended Operating Conditions ..................... 12
Supplies ................................................................... 97
7.4
Thermal Information ................................................ 13
12
Layout................................................................... 98
7.5
Electrical Characteristics......................................... 13
12.1
Layout Guidelines ................................................. 98
7.6
Timing Requirements: Serial Interface.................... 17
12.2
Layout Example .................................................... 99
7.7
Switching Characteristics: Serial Interface.............. 17
13
Device and Documentation Support ............... 100
7.8
Typical Characteristics ............................................ 18
13.1
Related Links ...................................................... 100
8
Parameter Measurement Information ................ 22
13.2
Community Resources........................................ 100
8.1
Noise Measurements .............................................. 22
13.3
Trademarks ......................................................... 100
9
Detailed Description ............................................ 24
13.4
Electrostatic Discharge Caution .......................... 100
9.1
Overview ................................................................. 24
13.5
Glossary .............................................................. 100
9.2
Functional Block Diagram ....................................... 25
14
Mechanical, Packaging, and Orderable
9.3
Feature Description................................................. 26
Information ......................................................... 100
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (January 2014) to Revision K
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changed text throughout data sheet for clarity ...................................................................................................................... 1
Added note to DAISY_IN pin ................................................................................................................................................. 8
Added note to DAISY_IN pin ............................................................................................................................................... 10
Changed Equation 3 ............................................................................................................................................................ 32
Changes from Revision I (January 2012) to Revision J
Page
Changed NC pin discription in Pin Assignments table ......................................................................................................... 10
Changed NC pin discription in Pin Assignments table ......................................................................................................... 10
Added graph of INTERNAL VREF DRIFT vs TEMPERATURE ............................................................................................. 21
Changed order of subsections in the Theory of Operation section ...................................................................................... 26
Changed single-ended input description to correct input range values ............................................................................... 30
Changed Figure 27 to show correct input range for single-ended inputs ............................................................................ 30
Changed Figure 28 to show correct input range for single-ended inputs ............................................................................ 30
Deleted text regarding large scale signal ............................................................................................................................. 31
Changed Figure 32 to provide a more stable external reference driver circuit .................................................................... 33
Updated Figure 57 ............................................................................................................................................................... 51
Added Figure 58 .................................................................................................................................................................. 52
Added discussion of SCLK/DRDY bus behavior to Data Ready (DRDY) section................................................................ 53
Added Figure 60 .................................................................................................................................................................. 53
2
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