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SN65DSI86-Q1 Datasheet(PDF) 4 Page - Texas Instruments

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Part # SN65DSI86-Q1
Description  MIPI DSI to eDP Bridge
Download  81 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN65DSI86-Q1 Datasheet(HTML) 4 Page - Texas Instruments

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background image
GND
VCC
TEST3
REFCLK
VCCIO
GPIO3
GPIO2
GPIO4
GPIO1
VCC
TEST1
50
51
52
53
54
49
56
57
58
59
60
TEST2
55
DACP
VCCA
DA1P
DA2N
DA1N
DA2P
DACN
GND
DA3N
DA3P
HPD
31
30
29
28
27
25
24
23
22
21
GND
26
4
5
8
6
7
9
10
11
47
46
45
44
43
42
40
39
41
2
3
1
12
38
37
48
13
14
15
16
DA0N
VCC
VCCA
DA0P
20
19
18
17
IRQ
VCC
VCCIO
GND
61
62
63
64
32
36
35
34
33
SN65DSI86-Q1
SLLSEJ5A – JULY 2014 – REVISED DECEMBER 2015
www.ti.com
6 Pin Configuration and Functions
PAP Package
64-Pin HTQFP
Top View
See Layout Guidelines for additional information.
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
DA0P
19
I
MIPI D-PHY Channel A Data Lane 0; data rate up to 1.5 Gbps.
DA0N
20
DA1P
21
I
MIPI D-PHY Channel A Data Lane 1; data rate up to 1.5 Gbps.
DA1N
22
DACP
24
MIPI D-PHY Channel A Clock Lane; operates up to 750MHz. Under proper conditions, this clock can
I
be used instead of REFCLK to feed DP_PLL
DACN
25
DA2P
27
I
MIPI D-PHY Channel A Data Lane 2; data rate up to 1.5 Gbps.
DA2N
28
DA3P
29
I
MIPI D-PHY Channel A Data Lane 3; data rate up to 1.5 Gbps.
DA3N
30
DB0P
4
I
MIPI D-PHY Channel B Data Lane 0; data rate up to 1.5 Gbps.
DB0N
5
DB1P
6
I
MIPI D-PHY Channel B Data Lane 1; data rate up to 1.5 Gbps.
DB1N
7
DBCP
8
I
MIPI D-PHY Channel B Clock Lane; operates up to 750 MHz.
DBCN
9
DB2P
10
I
MIPI D-PHY Channel B Data Lane 2; data rate up to 1.5 Gbps.
DB2N
11
4
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