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Q67060-S6307-A6 Datasheet(PDF) 2 Page - Infineon Technologies AG |
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Q67060-S6307-A6 Datasheet(HTML) 2 Page - Infineon Technologies AG |
2 / 15 page BTS 640 S2 Semiconductor Group Page 2 2003-Oct-01 Pin Symbol Function 1 ST Diagnostic feedback: open drain, invers to input level 2 GND Logic ground 3 IN Input, activates the power switch in case of logical high signal 4 Vbb Positive power supply voltage, the tab is shorted to this pin 5 IS Sense current output, proportional to the load current, zero in the case of current limitation of load current 6 & 7 OUT (Load, L) Output, protected high-side power output to the load. Both output pins have to be connected in parallel for operation according this spec (e.g. kILIS). Design the wiring for the max. short circuit current Maximum Ratings at Tj = 25 °C unless otherwise specified Parameter Symbol Values Unit Supply voltage (overvoltage protection see page 4) Vbb 43 V Supply voltage for full short circuit protection Tj Start=-40 ...+150°C Vbb 34 V Load dump protection1) VLoadDump = VA + Vs, VA = 13.5V RI2)= 2 Ω, RL= 1 Ω, td= 200 ms, IN= low or high VLoad dump3) 60 V Load current (Short circuit current, see page 5) IL self-limited A Operating temperature range Storage temperature range Tj Tstg -40 ...+150 -55 ...+150 °C Power dissipation (DC), TC ≤ 25 °C Ptot 85 W Inductive load switch-off energy dissipation, single pulse Vbb = 12V, Tj,start = 150°C, TC = 150°C const. IL = 12.6 A, ZL = 4,2 mH, 0 Ω: IL = 4 A, ZL = 330 mH, 0 Ω: EAS EAS 0,41 3,5 J Electrostatic discharge capability (ESD) IN: (Human Body Model) ST, IS: out to all other pins shorted: acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993 R=1.5k Ω; C=100pF VESD 1.0 4.0 8.0 kV Input voltage (DC) VIN -10 ... +16 V Current through input pin (DC) Current through status pin (DC) Current through current sense pin (DC) see internal circuit diagrams page 8 IIN IST IIS ±2.0 ±5.0 ±14 mA 1 ) Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins (a 150 Ω resistor in the GND connection is recommended). 2) RI = internal resistance of the load dump test pulse generator 3) VLoad dump is setup without the DUT connected to the generator according to ISO 7637-1 and DIN 40839 |
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