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SN65HVD266D Datasheet(PDF) 8 Page - Texas Instruments |
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SN65HVD266D Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 33 page  SN65HVD265, SN65HVD266, SN65HVD267 SLLSEI3A – SEPTEMBER 2013 – REVISED NOVEMBER 2015 www.ti.com 7.8 Switching Characteristics Over operating free-air temperature range (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT DEVICE SWITCHING CHARACTERISTICS Total loop delay, driver input (TXD) to tPROP(LOOP1) receiver output (RXD), recessive to 150 dominant See Figure 7, S = 0 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF Total loop delay, driver input (TXD) to ns tPROP(LOOP2) receiver output (RXD), dominant to 150 recessive Loop Delay Symmetry for 2Mbps CAN with See Figure 8 , S = 0 V, RL = 60Ω, CL = tREC(2Mbps) 400 550 Flexible Data Rate.(2) 100pF, CL(RXD) = 15pF, tBIT = 500ns Mode change time, from Normal to Silent IMODE See Figure 6 20 µS or from Silent to Normal DRIVER SWITCHING CHARACTERISTICS Propagation delay time, HIGH TXD to tpHR 50 70 Driver Recessive Propagation delay time, LOW TXD to tpLD 40 70 See Figure 4, S = 0 V, RL = 60 Ω, Driver Dominant ns CL = 100 pF, RCM = open tsk(p) Pulse skew (|tpHR - tpLD|) 10 tR Differential output signal rise time 10 30 tF Differential output signal fall time 17 30 Differential output signal rise time, tR(10k) 35 RL = 10 kΩ See Figure 4, S = 0 V, RL = 10 kΩ, CL ns = 10 pF, RCM = open Differential output signal fall time, tF(10k) 100 RL = 10 kΩ tTXD_DTO Dominant timeout(3) See Figure 9, RL = 60 Ω, CL = open 1175 3700 µs RECEIVER SWITCHING CHARACTERISTICS Propagation delay time, recessive input to tpRH 70 90 ns high output Propagation delay time, dominant input to tpDL 70 90 ns See Figure 5, CL(RXD) = 15 pF low output tR Output signal rise time 4 20 ns tF Output signal fall time 4 20 ns t(RXD_DTO) Receiver dominant time out (SN65HVD267 1380 4200 µs (4) only) See Figure 2, CL(RXD) = 15 pF (1) All typical values are at 25°C and supply voltages of VCC = 5 V and V(RXD) = 5 V, RL = 60 Ω. (2) Loop delay symmetry for CAN with flexible data rate or "improved CAN" for data rates in excess of 1Mbps. Specified in accordance with working draft 2Mbps specification from physical layer task force within CAN in Automation. (3) The TXD dominant timeout (t(TXD_DTO)) disables the driver of the transceiver once the TXD has been dominant longer than t(TXD_DTO), which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the t(TXD_DTO) minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11 / t(TXD_DTO) = 11 bits / 1175 µs = 9.4 kbps. (4) The RXD timeout (t(RXD_DTO)) disables the driver of the transceiver once the RXD has been dominant longer than t(RXD_DTO), which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant again after RXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on RXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the t(RXD_DTO) minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11 / t(RXD_DTO) = 11 bits / 1380 µs = 8 kbps. 8 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD265 SN65HVD266 SN65HVD267 |
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