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TPD4E02B04 Datasheet(PDF) 5 Page - Texas Instruments |
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TPD4E02B04 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 21 page  0 5 10 15 20 25 30 0 3 6 9 12 15 18 21 24 Voltage (V) C001 0 5 10 15 20 25 30 0 3 6 9 12 15 18 21 24 Voltage (V) C002 5 TPD4E02B04 www.ti.com SLVSD85A – NOVEMBER 2015 – REVISED FEBRUARY 2016 Product Folder Links: TPD4E02B04 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated (1) VBRF and VBRR are defined as the voltage when 1mA is applied in the positive-going direction, before the device latches into the snapback state (2) VHOLD is defined as the voltage when 1mA is applied in the negative-going direction, after the device has successfully latched into the snapback state 6.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VRWM Reverse stand-off voltage IIO < 10 nA -3.6 3.6 V VBRF Breakdown Voltage, any IO pin to GND(1) IIO = 1 mA, TA = 25°C 5.5 6.4 7.5 V VBRR Breakdown Voltage, GND to any IO pin(1) IIO = 1 mA, TA = 25°C -5.5 -6.4 -7.5 V VHOLD Holding voltage(2) IIO = 1 mA 5.8 V VCLAMP Clamping voltage IPP = 1 A, TLP, from IO to GND 6.6 V IPP = 5 A, TLP, from IO to GND 8.8 IPP = 1 A, TLP, from GND to IO 6.6 IPP = 5A, TLP, from GND to IO 8.8 ILEAK Leakage current, any IO to GND VIO = ±2.5 V 10 nA RDYN Dynamic Resistance IO to GND 0.47 Ω GND to IO 0.47 CL Line Capacitance VIO = 0 V, f = 1 MHz, IO to GND, TA = 25°C 0.27 0.37 pF ΔCL Variation of Line Capacitance Delta of capacitance between any two IO pins, VIO = 0 V, f = 1 MHz, TA = 25°C, GND = 0 V 0.01 0.07 pF CCROSS Channel to Channel Capacitance Capacitance from one IO to another, VIO = 0 V, f = 1 MHz, GND = 0 V 0.13 pF 6.6 Typical Characteristics Figure 1. Positive TLP Curve Figure 2. Negative TLP Curve |
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